[coreboot-gerrit] Change in coreboot[master]: Fix a typo on "mtrr"

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/25823


Change subject: Fix a typo on "mtrr"
......................................................................

Fix a typo on "mtrr"

Change "mttrs" to mtrrs.

Change-Id: I4e5930cdcba5e8f5366bb2d4ebbcb659c0c2eb27
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/drivers/intel/fsp1_1/include/fsp/romstage.h
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/broadwell/include/soc/romstage.h
M src/soc/intel/broadwell/romstage/romstage.c
M src/soc/intel/broadwell/romstage/stack.c
5 files changed, 9 insertions(+), 9 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/25823/1

diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index 892a653..d79be70 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -54,7 +54,7 @@
  *  16.  src/soc/intel/common/romstage.c/romstage_common - return
  *  17.  src/mainboard/.../romstage.c/mainboard_romstage_entry - return
  *  18.  src/soc/intel/common/romstage.c/romstage_main - return
- *  19.  src/soc/intel/common/stack.c/setup_stack_and_mttrs
+ *  19.  src/soc/intel/common/stack.c/setup_stack_and_mtrrs
  *  20.  src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup
  *       after call to romstage_main
  *  21.  FSP binary/TempRamExit
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 0e8710a..980064c 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -50,7 +50,7 @@
  * Because we can't use global variables the stack is used for allocations --
  * thus the need to call back and forth. */
 
-static void *setup_stack_and_mttrs(void);
+static void *setup_stack_and_mtrrs(void);
 
 static void program_base_addresses(void)
 {
@@ -131,7 +131,7 @@
 	/* Call into mainboard. */
 	mainboard_romstage_entry(&rp);
 
-	return setup_stack_and_mttrs();
+	return setup_stack_and_mtrrs();
 }
 
 static struct chipset_power_state power_state CAR_GLOBAL;
@@ -248,9 +248,9 @@
 	return stack;
 }
 
-/* setup_stack_and_mttrs() determines the stack to use after
+/* setup_stack_and_mtrrs() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use. */
-static void *setup_stack_and_mttrs(void)
+static void *setup_stack_and_mtrrs(void)
 {
 	int num_mtrrs;
 	uint32_t *slot;
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index eb4e097..e52004b 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -33,7 +33,7 @@
 			       uint32_t tsc_high);
 asmlinkage void romstage_after_car(void);
 void raminit(struct pei_data *pei_data);
-void *setup_stack_and_mttrs(void);
+void *setup_stack_and_mtrrs(void);
 
 struct chipset_power_state;
 struct chipset_power_state *fill_power_state(void);
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 025855b..8a3f291 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -80,7 +80,7 @@
 	/* Call into mainboard. */
 	mainboard_romstage_entry(&rp);
 
-	return setup_stack_and_mttrs();
+	return setup_stack_and_mtrrs();
 }
 
 /* Entry from the mainboard. */
diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c
index a6a4b4b..aa36e29 100644
--- a/src/soc/intel/broadwell/romstage/stack.c
+++ b/src/soc/intel/broadwell/romstage/stack.c
@@ -30,9 +30,9 @@
 	return stack;
 }
 
-/* setup_stack_and_mttrs() determines the stack to use after
+/* setup_stack_and_mtrrs() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use. */
-void *setup_stack_and_mttrs(void)
+void *setup_stack_and_mtrrs(void)
 {
 	int num_mtrrs;
 	uint32_t *slot;

-- 
To view, visit https://review.coreboot.org/25823
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4e5930cdcba5e8f5366bb2d4ebbcb659c0c2eb27
Gerrit-Change-Number: 25823
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180425/49fab02e/attachment.html>