<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25823">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Fix a typo on "mtrr"<br><br>Change "mttrs" to mtrrs.<br><br>Change-Id: I4e5930cdcba5e8f5366bb2d4ebbcb659c0c2eb27<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/drivers/intel/fsp1_1/include/fsp/romstage.h<br>M src/soc/intel/baytrail/romstage/romstage.c<br>M src/soc/intel/broadwell/include/soc/romstage.h<br>M src/soc/intel/broadwell/romstage/romstage.c<br>M src/soc/intel/broadwell/romstage/stack.c<br>5 files changed, 9 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/25823/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h</span><br><span>index 892a653..d79be70 100644</span><br><span>--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h</span><br><span>+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h</span><br><span>@@ -54,7 +54,7 @@</span><br><span> * 16. src/soc/intel/common/romstage.c/romstage_common - return</span><br><span> * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return</span><br><span> * 18. src/soc/intel/common/romstage.c/romstage_main - return</span><br><span style="color: hsl(0, 100%, 40%);">- * 19. src/soc/intel/common/stack.c/setup_stack_and_mttrs</span><br><span style="color: hsl(120, 100%, 40%);">+ * 19. src/soc/intel/common/stack.c/setup_stack_and_mtrrs</span><br><span> * 20. src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup</span><br><span> * after call to romstage_main</span><br><span> * 21. FSP binary/TempRamExit</span><br><span>diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c</span><br><span>index 0e8710a..980064c 100644</span><br><span>--- a/src/soc/intel/baytrail/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/baytrail/romstage/romstage.c</span><br><span>@@ -50,7 +50,7 @@</span><br><span> * Because we can't use global variables the stack is used for allocations --</span><br><span> * thus the need to call back and forth. */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void *setup_stack_and_mttrs(void);</span><br><span style="color: hsl(120, 100%, 40%);">+static void *setup_stack_and_mtrrs(void);</span><br><span> </span><br><span> static void program_base_addresses(void)</span><br><span> {</span><br><span>@@ -131,7 +131,7 @@</span><br><span> /* Call into mainboard. */</span><br><span> mainboard_romstage_entry(&rp);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- return setup_stack_and_mttrs();</span><br><span style="color: hsl(120, 100%, 40%);">+ return setup_stack_and_mtrrs();</span><br><span> }</span><br><span> </span><br><span> static struct chipset_power_state power_state CAR_GLOBAL;</span><br><span>@@ -248,9 +248,9 @@</span><br><span> return stack;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* setup_stack_and_mttrs() determines the stack to use after</span><br><span style="color: hsl(120, 100%, 40%);">+/* setup_stack_and_mtrrs() determines the stack to use after</span><br><span> * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span style="color: hsl(0, 100%, 40%);">-static void *setup_stack_and_mttrs(void)</span><br><span style="color: hsl(120, 100%, 40%);">+static void *setup_stack_and_mtrrs(void)</span><br><span> {</span><br><span> int num_mtrrs;</span><br><span> uint32_t *slot;</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h</span><br><span>index eb4e097..e52004b 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/romstage.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/romstage.h</span><br><span>@@ -33,7 +33,7 @@</span><br><span> uint32_t tsc_high);</span><br><span> asmlinkage void romstage_after_car(void);</span><br><span> void raminit(struct pei_data *pei_data);</span><br><span style="color: hsl(0, 100%, 40%);">-void *setup_stack_and_mttrs(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void *setup_stack_and_mtrrs(void);</span><br><span> </span><br><span> struct chipset_power_state;</span><br><span> struct chipset_power_state *fill_power_state(void);</span><br><span>diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c</span><br><span>index 025855b..8a3f291 100644</span><br><span>--- a/src/soc/intel/broadwell/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/broadwell/romstage/romstage.c</span><br><span>@@ -80,7 +80,7 @@</span><br><span> /* Call into mainboard. */</span><br><span> mainboard_romstage_entry(&rp);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- return setup_stack_and_mttrs();</span><br><span style="color: hsl(120, 100%, 40%);">+ return setup_stack_and_mtrrs();</span><br><span> }</span><br><span> </span><br><span> /* Entry from the mainboard. */</span><br><span>diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c</span><br><span>index a6a4b4b..aa36e29 100644</span><br><span>--- a/src/soc/intel/broadwell/romstage/stack.c</span><br><span>+++ b/src/soc/intel/broadwell/romstage/stack.c</span><br><span>@@ -30,9 +30,9 @@</span><br><span> return stack;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* setup_stack_and_mttrs() determines the stack to use after</span><br><span style="color: hsl(120, 100%, 40%);">+/* setup_stack_and_mtrrs() determines the stack to use after</span><br><span> * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span style="color: hsl(0, 100%, 40%);">-void *setup_stack_and_mttrs(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void *setup_stack_and_mtrrs(void)</span><br><span> {</span><br><span> int num_mtrrs;</span><br><span> uint32_t *slot;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25823">change 25823</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25823"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4e5930cdcba5e8f5366bb2d4ebbcb659c0c2eb27 </div>
<div style="display:none"> Gerrit-Change-Number: 25823 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>