[coreboot-gerrit] Change in coreboot[master]: [WIP] soc/intel/cannonlake: Use bootblock common stage
Bora Guvendik (Code Review)
gerrit at coreboot.org
Wed Apr 25 01:27:05 CEST 2018
Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/25811
Change subject: [WIP] soc/intel/cannonlake: Use bootblock common stage
......................................................................
[WIP] soc/intel/cannonlake: Use bootblock common stage
Change apollolake bootcode to use common bootblock stage
Change-Id: I4397c6d599a9f4ef235755835db3f4d22f81674e
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
D src/soc/intel/cannonlake/bootblock/bootblock.c
M src/soc/intel/cannonlake/bootblock/cpu.c
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
D src/soc/intel/cannonlake/include/soc/bootblock.h
7 files changed, 49 insertions(+), 250 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/25811/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index ebf6741..630a9f3 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -43,6 +43,7 @@
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BASECODE
+ select SOC_INTEL_COMMON_BASECODE_BOOTBLOCK
select SOC_INTEL_COMMON_BASECODE_LOCKDOWN
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 0e73c14..064c64d 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -8,7 +8,6 @@
subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
-bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cpu.c
bootblock-y += bootblock/pch.c
bootblock-y += pmutil.c
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
deleted file mode 100644
index 9db9a0f..0000000
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Intel Corporation..
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <bootblock_common.h>
-#include <intelblocks/gspi.h>
-#include <soc/bootblock.h>
-#include <soc/iomap.h>
-#include <soc/pch.h>
-
-asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
-{
- /* Call lib/bootblock.c main */
- bootblock_main_with_timestamp(base_timestamp);
-}
-
-void bootblock_soc_early_init(void)
-{
- bootblock_systemagent_early_init();
- bootblock_pch_early_init();
- bootblock_cpu_init();
- pch_early_iorange_init();
- if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM))
- pch_uart_init();
-}
-
-void bootblock_soc_init(void)
-{
- report_platform_info();
- pch_early_init();
-}
diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c
index 3ebe1e4..a828448 100644
--- a/src/soc/intel/cannonlake/bootblock/cpu.c
+++ b/src/soc/intel/cannonlake/bootblock/cpu.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,12 +14,13 @@
* GNU General Public License for more details.
*/
-#include <intelblocks/cpulib.h>
+#include <intelbasecode/bootblock.h>
#include <intelblocks/fast_spi.h>
-#include <soc/bootblock.h>
-void bootblock_cpu_init(void)
+void bootblock_cpu_early_init(void)
{
+ fast_spi_early_init(SPI_BASE_ADDRESS);
+
/* Temporarily cache the memory-mapped boot media. */
if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&
IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 8e4f7fd..771df1b 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -15,6 +15,7 @@
*/
#include <device/device.h>
+#include <intelbasecode/bootblock.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
@@ -22,7 +23,6 @@
#include <intelblocks/rtc.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/smbus.h>
-#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/p2sb.h>
@@ -92,18 +92,27 @@
write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);
}
-void bootblock_pch_early_init(void)
+static void pch_early_iorange_init(void)
{
- fast_spi_early_init(SPI_BASE_ADDRESS);
- gspi_early_bar_init();
- enable_p2sbbar();
- /*
- * Enabling PWRM Base for accessing
- * Global Reset Cause Register.
- */
- soc_config_pwrmbase();
-}
+ uint16_t dec_rng, dec_en = 0;
+ /* IO Decode Range */
+ if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) &&
+ IS_ENABLED(CONFIG_UART_DEBUG)) {
+ dec_rng = COMA_RANGE | (COMB_RANGE << 4);
+ dec_en = COMA_LPC_EN | COMB_LPC_EN;
+ pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, dec_rng);
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOD, dec_rng);
+ }
+
+ /* IO Decode Enable */
+ dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN;
+ pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);
+
+ /* Program generic IO Decode Range */
+ pch_enable_lpc();
+}
static void soc_config_acpibase(void)
{
@@ -158,29 +167,19 @@
outw(tcocnt, tcobase + TCO1_CNT);
}
-void pch_early_iorange_init(void)
+void bootblock_pch_early_init(void)
{
- uint16_t dec_rng, dec_en = 0;
-
- /* IO Decode Range */
- if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) &&
- IS_ENABLED(CONFIG_UART_DEBUG)) {
- dec_rng = COMA_RANGE | (COMB_RANGE << 4);
- dec_en = COMA_LPC_EN | COMB_LPC_EN;
- pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, dec_rng);
- pcr_write16(PID_DMI, PCR_DMI_LPCIOD, dec_rng);
- }
-
- /* IO Decode Enable */
- dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN;
- pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);
- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);
-
- /* Program generic IO Decode Range */
- pch_enable_lpc();
+ gspi_early_bar_init();
+ enable_p2sbbar();
+ /*
+ * Enabling PWRM Base for accessing
+ * Global Reset Cause Register.
+ */
+ soc_config_pwrmbase();
+ pch_early_iorange_init();
}
-void pch_early_init(void)
+void bootblock_pch_init(void)
{
/*
* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index c81e534..604e597 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -14,51 +14,31 @@
* GNU General Public License for more details.
*/
-#include <arch/cpu.h>
#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <device/pci.h>
#include <device/pci_ids.h>
+#include <intelbasecode/report_platform.h>
#include <intelblocks/mp_init.h>
-#include <soc/bootblock.h>
-#include <soc/pch.h>
-#include <soc/pci_devs.h>
-#include <string.h>
-#define BIOS_SIGN_ID 0x8B
-static struct {
- u32 cpuid;
- const char *name;
-} cpu_table[] = {
+struct cpu_info cpu_table[] = {
{ CPUID_CANNONLAKE_A0, "Cannonlake A0" },
{ CPUID_CANNONLAKE_B0, "Cannonlake B0" },
{ CPUID_CANNONLAKE_C0, "Cannonlake C0" },
{ CPUID_CANNONLAKE_D0, "Cannonlake D0" },
};
-static struct {
- u16 mchid;
- const char *name;
-} mch_table[] = {
+struct mch_info mch_table[] = {
{ PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" },
{ PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" },
};
-static struct {
- u16 lpcid;
- const char *name;
-} pch_table[] = {
+struct pch_info pch_table[] = {
{ PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },
{ PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },
{ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },
};
-static struct {
- u16 igdid;
- const char *name;
-} igd_table[] = {
+struct igd_info igd_table[] = {
{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1, "Cannonlake ULX GT2" },
{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2, "Cannonlake ULX GT1.5" },
{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3, "Cannonlake ULX GT1" },
@@ -69,131 +49,22 @@
{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },
};
-static uint8_t get_dev_revision(device_t dev)
+struct cpu_info* soc_get_cpu_id_table(void)
{
- return pci_read_config8(dev, PCI_REVISION_ID);
+ return cpu_table;
}
-static uint16_t get_dev_id(device_t dev)
+struct mch_info* soc_get_mch_id_table(void)
{
- return pci_read_config16(dev, PCI_DEVICE_ID);
+ return mch_table;
}
-static void report_cpu_info(void)
+struct pch_info* soc_get_pch_id_table(void)
{
- struct cpuid_result cpuidr;
- u32 i, index;
- char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
- int vt, txt, aes;
- msr_t microcode_ver;
- static const char * const mode[] = {"NOT ", ""};
- const char *cpu_type = "Unknown";
- u32 p[13];
-
- index = 0x80000000;
- cpuidr = cpuid(index);
- if (cpuidr.eax < 0x80000004) {
- strcpy(cpu_string, "Platform info not available");
- } else {
- int j=0;
-
- for (i = 2; i <= 4; i++) {
- cpuidr = cpuid(index + i);
- p[j++] = cpuidr.eax;
- p[j++] = cpuidr.ebx;
- p[j++] = cpuidr.ecx;
- p[j++] = cpuidr.edx;
- }
- p[12]=0;
- cpu_name = (char *)p;
- }
- /* Skip leading spaces in CPU name string */
- while (cpu_name[0] == ' ')
- cpu_name++;
-
- microcode_ver.lo = 0;
- microcode_ver.hi = 0;
- wrmsr(BIOS_SIGN_ID, microcode_ver);
- cpuidr = cpuid(1);
- microcode_ver = rdmsr(BIOS_SIGN_ID);
-
- /* Look for string to match the name */
- for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
- if (cpu_table[i].cpuid == cpuidr.eax) {
- cpu_type = cpu_table[i].name;
- break;
- }
- }
-
- printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
- printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
- cpuidr.eax, cpu_type, microcode_ver.hi);
-
- aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
- txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
- vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
- printk(BIOS_DEBUG,
- "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
- mode[aes], mode[txt], mode[vt]);
+ return pch_table;
}
-static void report_mch_info(void)
+struct igd_info* soc_get_igd_id_table(void)
{
- int i;
- device_t dev = SA_DEV_ROOT;
- uint16_t mchid = get_dev_id(dev);
- uint8_t mch_revision = get_dev_revision(dev);
- const char *mch_type = "Unknown";
-
- for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
- if (mch_table[i].mchid == mchid) {
- mch_type = mch_table[i].name;
- break;
- }
- }
-
- printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
- mchid, mch_revision, mch_type);
-}
-
-static void report_pch_info(void)
-{
- int i;
- device_t dev = PCH_DEV_LPC;
- uint16_t lpcid = get_dev_id(dev);
- const char *pch_type = "Unknown";
-
- for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
- if (pch_table[i].lpcid == lpcid) {
- pch_type = pch_table[i].name;
- break;
- }
- }
- printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
- lpcid, get_dev_revision(dev), pch_type);
-}
-
-static void report_igd_info(void)
-{
- int i;
- device_t dev = SA_DEV_IGD;
- uint16_t igdid = get_dev_id(dev);
- const char *igd_type = "Unknown";
-
- for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
- if (igd_table[i].igdid == igdid) {
- igd_type = igd_table[i].name;
- break;
- }
- }
- printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
- igdid, get_dev_revision(dev), igd_type);
-}
-
-void report_platform_info(void)
-{
- report_cpu_info();
- report_mch_info();
- report_pch_info();
- report_igd_info();
+ return igd_table;
}
diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h
deleted file mode 100644
index a5c3c32..0000000
--- a/src/soc/intel/cannonlake/include/soc/bootblock.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_CANNONLAKE_BOOTBLOCK_H_
-#define _SOC_CANNONLAKE_BOOTBLOCK_H_
-
-#include <intelblocks/systemagent.h>
-
-/* Bootblock pre console init programming */
-void bootblock_cpu_init(void);
-void bootblock_pch_early_init(void);
-
-/* Bootblock post console init programming */
-void pch_early_init(void);
-void pch_early_iorange_init(void);
-void report_platform_info(void);
-
-#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4397c6d599a9f4ef235755835db3f4d22f81674e
Gerrit-Change-Number: 25811
Gerrit-PatchSet: 1
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
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