<p>Bora Guvendik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25811">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP] soc/intel/cannonlake: Use bootblock common stage<br><br>Change apollolake bootcode to use common bootblock stage<br><br>Change-Id: I4397c6d599a9f4ef235755835db3f4d22f81674e<br>Signed-off-by: Bora Guvendik <bora.guvendik@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>D src/soc/intel/cannonlake/bootblock/bootblock.c<br>M src/soc/intel/cannonlake/bootblock/cpu.c<br>M src/soc/intel/cannonlake/bootblock/pch.c<br>M src/soc/intel/cannonlake/bootblock/report_platform.c<br>D src/soc/intel/cannonlake/include/soc/bootblock.h<br>7 files changed, 49 insertions(+), 250 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/25811/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index ebf6741..630a9f3 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -43,6 +43,7 @@</span><br><span> select SOC_INTEL_COMMON</span><br><span> select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE</span><br><span> select SOC_INTEL_COMMON_BASECODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BASECODE_BOOTBLOCK</span><br><span> select SOC_INTEL_COMMON_BASECODE_LOCKDOWN</span><br><span> select SOC_INTEL_COMMON_BLOCK</span><br><span> select SOC_INTEL_COMMON_BLOCK_ACPI</span><br><span>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>index 0e73c14..064c64d 100644</span><br><span>--- a/src/soc/intel/cannonlake/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>@@ -8,7 +8,6 @@</span><br><span> subdirs-y += ../../../cpu/x86/smm</span><br><span> subdirs-y += ../../../cpu/x86/tsc</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += bootblock/bootblock.c</span><br><span> bootblock-y += bootblock/cpu.c</span><br><span> bootblock-y += bootblock/pch.c</span><br><span> bootblock-y += pmutil.c</span><br><span>diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c</span><br><span>deleted file mode 100644</span><br><span>index 9db9a0f..0000000</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/bootblock.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,42 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corporation..</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <bootblock_common.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/gspi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/bootblock.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/iomap.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pch.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-asmlinkage void bootblock_c_entry(uint64_t base_timestamp)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Call lib/bootblock.c main */</span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_main_with_timestamp(base_timestamp);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_soc_early_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_systemagent_early_init();</span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_pch_early_init();</span><br><span style="color: hsl(0, 100%, 40%);">- bootblock_cpu_init();</span><br><span style="color: hsl(0, 100%, 40%);">- pch_early_iorange_init();</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM))</span><br><span style="color: hsl(0, 100%, 40%);">- pch_uart_init();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_soc_init(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- report_platform_info();</span><br><span style="color: hsl(0, 100%, 40%);">- pch_early_init();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c</span><br><span>index 3ebe1e4..a828448 100644</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/cpu.c</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/cpu.c</span><br><span>@@ -2,7 +2,7 @@</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span> * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -14,12 +14,13 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/cpulib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/bootblock.h></span><br><span> #include <intelblocks/fast_spi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/bootblock.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_cpu_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_cpu_early_init(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ fast_spi_early_init(SPI_BASE_ADDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Temporarily cache the memory-mapped boot media. */</span><br><span> if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&</span><br><span> IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))</span><br><span>diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>index 8e4f7fd..771df1b 100644</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/bootblock.h></span><br><span> #include <intelblocks/fast_spi.h></span><br><span> #include <intelblocks/gspi.h></span><br><span> #include <intelblocks/lpc_lib.h></span><br><span>@@ -22,7 +23,6 @@</span><br><span> #include <intelblocks/rtc.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span> #include <intelblocks/smbus.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/bootblock.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/lpc.h></span><br><span> #include <soc/p2sb.h></span><br><span>@@ -92,18 +92,27 @@</span><br><span> write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_pch_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_early_iorange_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_early_init(SPI_BASE_ADDRESS);</span><br><span style="color: hsl(0, 100%, 40%);">- gspi_early_bar_init();</span><br><span style="color: hsl(0, 100%, 40%);">- enable_p2sbbar();</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Enabling PWRM Base for accessing</span><br><span style="color: hsl(0, 100%, 40%);">- * Global Reset Cause Register.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- soc_config_pwrmbase();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t dec_rng, dec_en = 0;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* IO Decode Range */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ IS_ENABLED(CONFIG_UART_DEBUG)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ dec_rng = COMA_RANGE | (COMB_RANGE << 4);</span><br><span style="color: hsl(120, 100%, 40%);">+ dec_en = COMA_LPC_EN | COMB_LPC_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, dec_rng);</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write16(PID_DMI, PCR_DMI_LPCIOD, dec_rng);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IO Decode Enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program generic IO Decode Range */</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_enable_lpc();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span> </span><br><span> static void soc_config_acpibase(void)</span><br><span> {</span><br><span>@@ -158,29 +167,19 @@</span><br><span> outw(tcocnt, tcobase + TCO1_CNT);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void pch_early_iorange_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_pch_early_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t dec_rng, dec_en = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* IO Decode Range */</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) &&</span><br><span style="color: hsl(0, 100%, 40%);">- IS_ENABLED(CONFIG_UART_DEBUG)) {</span><br><span style="color: hsl(0, 100%, 40%);">- dec_rng = COMA_RANGE | (COMB_RANGE << 4);</span><br><span style="color: hsl(0, 100%, 40%);">- dec_en = COMA_LPC_EN | COMB_LPC_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, dec_rng);</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write16(PID_DMI, PCR_DMI_LPCIOD, dec_rng);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* IO Decode Enable */</span><br><span style="color: hsl(0, 100%, 40%);">- dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Program generic IO Decode Range */</span><br><span style="color: hsl(0, 100%, 40%);">- pch_enable_lpc();</span><br><span style="color: hsl(120, 100%, 40%);">+ gspi_early_bar_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_p2sbbar();</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enabling PWRM Base for accessing</span><br><span style="color: hsl(120, 100%, 40%);">+ * Global Reset Cause Register.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_config_pwrmbase();</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_early_iorange_init();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void pch_early_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+void bootblock_pch_init(void)</span><br><span> {</span><br><span> /*</span><br><span> * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,</span><br><span>diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c</span><br><span>index c81e534..604e597 100644</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/report_platform.c</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c</span><br><span>@@ -14,51 +14,31 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/cpu.h></span><br><span> #include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci.h></span><br><span> #include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/report_platform.h></span><br><span> #include <intelblocks/mp_init.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/bootblock.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pch.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pci_devs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define BIOS_SIGN_ID 0x8B</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 cpuid;</span><br><span style="color: hsl(0, 100%, 40%);">- const char *name;</span><br><span style="color: hsl(0, 100%, 40%);">-} cpu_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+struct cpu_info cpu_table[] = {</span><br><span> { CPUID_CANNONLAKE_A0, "Cannonlake A0" },</span><br><span> { CPUID_CANNONLAKE_B0, "Cannonlake B0" },</span><br><span> { CPUID_CANNONLAKE_C0, "Cannonlake C0" },</span><br><span> { CPUID_CANNONLAKE_D0, "Cannonlake D0" },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct {</span><br><span style="color: hsl(0, 100%, 40%);">- u16 mchid;</span><br><span style="color: hsl(0, 100%, 40%);">- const char *name;</span><br><span style="color: hsl(0, 100%, 40%);">-} mch_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+struct mch_info mch_table[] = {</span><br><span> { PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" },</span><br><span> { PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct {</span><br><span style="color: hsl(0, 100%, 40%);">- u16 lpcid;</span><br><span style="color: hsl(0, 100%, 40%);">- const char *name;</span><br><span style="color: hsl(0, 100%, 40%);">-} pch_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+struct pch_info pch_table[] = {</span><br><span> { PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },</span><br><span> { PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },</span><br><span> { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static struct {</span><br><span style="color: hsl(0, 100%, 40%);">- u16 igdid;</span><br><span style="color: hsl(0, 100%, 40%);">- const char *name;</span><br><span style="color: hsl(0, 100%, 40%);">-} igd_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+struct igd_info igd_table[] = {</span><br><span> { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1, "Cannonlake ULX GT2" },</span><br><span> { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2, "Cannonlake ULX GT1.5" },</span><br><span> { PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3, "Cannonlake ULX GT1" },</span><br><span>@@ -69,131 +49,22 @@</span><br><span> { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static uint8_t get_dev_revision(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+struct cpu_info* soc_get_cpu_id_table(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return pci_read_config8(dev, PCI_REVISION_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ return cpu_table;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static uint16_t get_dev_id(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+struct mch_info* soc_get_mch_id_table(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return pci_read_config16(dev, PCI_DEVICE_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+ return mch_table;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void report_cpu_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+struct pch_info* soc_get_pch_id_table(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- struct cpuid_result cpuidr;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 i, index;</span><br><span style="color: hsl(0, 100%, 40%);">- char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */</span><br><span style="color: hsl(0, 100%, 40%);">- int vt, txt, aes;</span><br><span style="color: hsl(0, 100%, 40%);">- msr_t microcode_ver;</span><br><span style="color: hsl(0, 100%, 40%);">- static const char * const mode[] = {"NOT ", ""};</span><br><span style="color: hsl(0, 100%, 40%);">- const char *cpu_type = "Unknown";</span><br><span style="color: hsl(0, 100%, 40%);">- u32 p[13];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- index = 0x80000000;</span><br><span style="color: hsl(0, 100%, 40%);">- cpuidr = cpuid(index);</span><br><span style="color: hsl(0, 100%, 40%);">- if (cpuidr.eax < 0x80000004) {</span><br><span style="color: hsl(0, 100%, 40%);">- strcpy(cpu_string, "Platform info not available");</span><br><span style="color: hsl(0, 100%, 40%);">- } else {</span><br><span style="color: hsl(0, 100%, 40%);">- int j=0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 2; i <= 4; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- cpuidr = cpuid(index + i);</span><br><span style="color: hsl(0, 100%, 40%);">- p[j++] = cpuidr.eax;</span><br><span style="color: hsl(0, 100%, 40%);">- p[j++] = cpuidr.ebx;</span><br><span style="color: hsl(0, 100%, 40%);">- p[j++] = cpuidr.ecx;</span><br><span style="color: hsl(0, 100%, 40%);">- p[j++] = cpuidr.edx;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- p[12]=0;</span><br><span style="color: hsl(0, 100%, 40%);">- cpu_name = (char *)p;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- /* Skip leading spaces in CPU name string */</span><br><span style="color: hsl(0, 100%, 40%);">- while (cpu_name[0] == ' ')</span><br><span style="color: hsl(0, 100%, 40%);">- cpu_name++;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- microcode_ver.lo = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- microcode_ver.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(BIOS_SIGN_ID, microcode_ver);</span><br><span style="color: hsl(0, 100%, 40%);">- cpuidr = cpuid(1);</span><br><span style="color: hsl(0, 100%, 40%);">- microcode_ver = rdmsr(BIOS_SIGN_ID);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Look for string to match the name */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (cpu_table[i].cpuid == cpuidr.eax) {</span><br><span style="color: hsl(0, 100%, 40%);">- cpu_type = cpu_table[i].name;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- cpuidr.eax, cpu_type, microcode_ver.hi);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;</span><br><span style="color: hsl(0, 100%, 40%);">- txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;</span><br><span style="color: hsl(0, 100%, 40%);">- vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG,</span><br><span style="color: hsl(0, 100%, 40%);">- "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",</span><br><span style="color: hsl(0, 100%, 40%);">- mode[aes], mode[txt], mode[vt]);</span><br><span style="color: hsl(120, 100%, 40%);">+ return pch_table;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void report_mch_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+struct igd_info* soc_get_igd_id_table(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t mchid = get_dev_id(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t mch_revision = get_dev_revision(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- const char *mch_type = "Unknown";</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(mch_table); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (mch_table[i].mchid == mchid) {</span><br><span style="color: hsl(0, 100%, 40%);">- mch_type = mch_table[i].name;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",</span><br><span style="color: hsl(0, 100%, 40%);">- mchid, mch_revision, mch_type);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void report_pch_info(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCH_DEV_LPC;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t lpcid = get_dev_id(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- const char *pch_type = "Unknown";</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(pch_table); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (pch_table[i].lpcid == lpcid) {</span><br><span style="color: hsl(0, 100%, 40%);">- pch_type = pch_table[i].name;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",</span><br><span style="color: hsl(0, 100%, 40%);">- lpcid, get_dev_revision(dev), pch_type);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void report_igd_info(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = SA_DEV_IGD;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t igdid = get_dev_id(dev);</span><br><span style="color: hsl(0, 100%, 40%);">- const char *igd_type = "Unknown";</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = 0; i < ARRAY_SIZE(igd_table); i++) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (igd_table[i].igdid == igdid) {</span><br><span style="color: hsl(0, 100%, 40%);">- igd_type = igd_table[i].name;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",</span><br><span style="color: hsl(0, 100%, 40%);">- igdid, get_dev_revision(dev), igd_type);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void report_platform_info(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- report_cpu_info();</span><br><span style="color: hsl(0, 100%, 40%);">- report_mch_info();</span><br><span style="color: hsl(0, 100%, 40%);">- report_pch_info();</span><br><span style="color: hsl(0, 100%, 40%);">- report_igd_info();</span><br><span style="color: hsl(120, 100%, 40%);">+ return igd_table;</span><br><span> }</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/bootblock.h b/src/soc/intel/cannonlake/include/soc/bootblock.h</span><br><span>deleted file mode 100644</span><br><span>index a5c3c32..0000000</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/bootblock.h</span><br><span>+++ /dev/null</span><br><span>@@ -1,30 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corporation</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#ifndef _SOC_CANNONLAKE_BOOTBLOCK_H_</span><br><span style="color: hsl(0, 100%, 40%);">-#define _SOC_CANNONLAKE_BOOTBLOCK_H_</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/systemagent.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Bootblock pre console init programming */</span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_cpu_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void bootblock_pch_early_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Bootblock post console init programming */</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_early_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_early_iorange_init(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void report_platform_info(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25811">change 25811</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25811"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4397c6d599a9f4ef235755835db3f4d22f81674e </div>
<div style="display:none"> Gerrit-Change-Number: 25811 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Bora Guvendik <bora.guvendik@intel.com> </div>