[coreboot-gerrit] Change in coreboot[master]: [WIP]soc/intel/common: Add common code to report platform information
Bora Guvendik (Code Review)
gerrit at coreboot.org
Tue Apr 24 23:19:07 CEST 2018
Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/25810
Change subject: [WIP]soc/intel/common: Add common code to report platform information
......................................................................
[WIP]soc/intel/common: Add common code to report platform information
Add common code so that all SoC can display CPU, MCH, PCH and
IGD information if SoC provides the necessary tables.
Change-Id: Id1497b72f784db00a334544f6c5ddc2774049107
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
M src/soc/intel/common/basecode/bootblock/Kconfig
M src/soc/intel/common/basecode/bootblock/Makefile.inc
M src/soc/intel/common/basecode/bootblock/bootblock.c
A src/soc/intel/common/basecode/bootblock/report_platform.c
A src/soc/intel/common/basecode/include/intelbasecode/report_platform.h
5 files changed, 269 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/25810/1
diff --git a/src/soc/intel/common/basecode/bootblock/Kconfig b/src/soc/intel/common/basecode/bootblock/Kconfig
index 754f4a3..2f22550 100644
--- a/src/soc/intel/common/basecode/bootblock/Kconfig
+++ b/src/soc/intel/common/basecode/bootblock/Kconfig
@@ -10,4 +10,10 @@
def_bool y
select SOC_INTEL_COMMON_BLOCK_SA
+config BOOTBLOCK_REPORT_PLATFORM_INFO
+ bool
+ default n
+ help
+ Report CPU, MCH, PCH, IGD information during boot
+
endif
diff --git a/src/soc/intel/common/basecode/bootblock/Makefile.inc b/src/soc/intel/common/basecode/bootblock/Makefile.inc
index 854196a..ae9ee48 100644
--- a/src/soc/intel/common/basecode/bootblock/Makefile.inc
+++ b/src/soc/intel/common/basecode/bootblock/Makefile.inc
@@ -1 +1,2 @@
bootblock-$(CONFIG_SOC_INTEL_COMMON_BASECODE_BOOTBLOCK) += bootblock.c
+bootblock-$(BOOTBLOCK_REPORT_PLATFORM_INFO) += report_platform.c
diff --git a/src/soc/intel/common/basecode/bootblock/bootblock.c b/src/soc/intel/common/basecode/bootblock/bootblock.c
index 3ccf9e8..184051b 100644
--- a/src/soc/intel/common/basecode/bootblock/bootblock.c
+++ b/src/soc/intel/common/basecode/bootblock/bootblock.c
@@ -15,6 +15,7 @@
#include <bootblock_common.h>
#include <intelbasecode/bootblock.h>
+#include <intelbasecode/report_platform.h>
#include <soc/pch.h>
/*
@@ -60,6 +61,10 @@
void bootblock_soc_init(void)
{
+ /* Get Platform details - SA, PCH, MCH, CPU etc */
+ if (IS_ENABLED(CONFIG_BOOTBLOCK_REPORT_PLATFORM_INFO))
+ report_platform_info();
+
bootblock_cpu_init();
bootblock_pch_init();
diff --git a/src/soc/intel/common/basecode/bootblock/report_platform.c b/src/soc/intel/common/basecode/bootblock/report_platform.c
new file mode 100644
index 0000000..d6fd7c9
--- /dev/null
+++ b/src/soc/intel/common/basecode/bootblock/report_platform.c
@@ -0,0 +1,203 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <intelbasecode/repot_platfom.h>
+#include <intelblocks/mp_init.h>
+#include <soc/bootblock.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <string.h>
+
+#define BIOS_SIGN_ID 0x8B
+
+__attribute__((weak)) struct cpu_info* soc_get_cpu_table(void)
+{
+ /* return NULL for this dummy API */
+ return NULL
+}
+
+__attribute__((weak)) struct mch_info* soc_get_mch_table(void)
+{
+ /* return NULL for this dummy API */
+ return NULL
+}
+
+__attribute__((weak)) struct pch_info* soc_get_pch_table(void)
+{
+ /* return NULL for this dummy API */
+ return NULL
+}
+
+__attribute__((weak)) struct igd_info* soc_get_igd_table(void)
+{
+ /* return NULL for this dummy API */
+ return NULL
+}
+
+static uint8_t get_dev_revision(device_t dev)
+{
+ return pci_read_config8(dev, PCI_REVISION_ID);
+}
+
+static uint16_t get_dev_id(device_t dev)
+{
+ return pci_read_config16(dev, PCI_DEVICE_ID);
+}
+
+static void report_cpu_info(struct cpu_info* cpu_info_table)
+{
+ struct cpuid_result cpuidr;
+ u32 i, index, t = 0;
+ char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
+ int vt, txt, aes;
+ msr_t microcode_ver;
+ static const char * const mode[] = {"NOT ", ""};
+ const char *cpu_type = "Unknown";
+ u32 p[13];
+
+ index = 0x80000000;
+ cpuidr = cpuid(index);
+ if (cpuidr.eax < 0x80000004) {
+ strcpy(cpu_string, "Platform info not available");
+ } else {
+ int j=0;
+
+ for (i = 2; i <= 4; i++) {
+ cpuidr = cpuid(index + i);
+ p[j++] = cpuidr.eax;
+ p[j++] = cpuidr.ebx;
+ p[j++] = cpuidr.ecx;
+ p[j++] = cpuidr.edx;
+ }
+ p[12]=0;
+ cpu_name = (char *)p;
+ }
+ /* Skip leading spaces in CPU name string */
+ while (cpu_name[0] == ' ')
+ cpu_name++;
+
+ microcode_ver.lo = 0;
+ microcode_ver.hi = 0;
+ wrmsr(BIOS_SIGN_ID, microcode_ver);
+ cpuidr = cpuid(1);
+ microcode_ver = rdmsr(BIOS_SIGN_ID);
+
+ /* Look for string to match the name */
+ while (cpu_info_table != NULL) {
+ if (cpu_info_table[t].cpuid == cpuidr.eax) {
+ cpu_type = cpu_info_table[t].name;
+ break;
+ }
+ t++;
+ cpu_info_table++;
+ }
+
+ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
+ printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
+ cpuidr.eax, cpu_type, microcode_ver.hi);
+
+ aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
+ txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
+ vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
+ printk(BIOS_DEBUG,
+ "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
+ mode[aes], mode[txt], mode[vt]);
+}
+
+static void report_mch_info(struct mch_info* mch_info_table)
+{
+ int i = 0;
+ device_t dev = SA_DEV_ROOT;
+ uint16_t mchid = get_dev_id(dev);
+ uint8_t mch_revision = get_dev_revision(dev);
+ const char *mch_type = "Unknown";
+
+ while (mch_info_table != NULL) {
+ if (mch_info_table[i].mchid == mchid) {
+ mch_type = mch_info_table[i].name;
+ break;
+ }
+ i++;
+ mch_info_table++;
+ }
+
+ printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
+ mchid, mch_revision, mch_type);
+}
+
+static void report_pch_info(struct pch_info* pch_info_table)
+{
+ int i = 0;
+ device_t dev = PCH_DEV_LPC;
+ uint16_t lpcid = get_dev_id(dev);
+ const char *pch_type = "Unknown";
+
+ while (pch_info_table != NULL) {
+ if (pch_info_table[i].lpcid == lpcid) {
+ pch_type = pch_info_table[i].name;
+ break;
+ }
+ i++;
+ pch_info_table++;
+ }
+ printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
+ lpcid, get_dev_revision(dev), pch_type);
+}
+
+static void report_igd_info(struct igd_info* igd_info_table)
+{
+ int i = 0;
+ device_t dev = SA_DEV_IGD;
+ uint16_t igdid = get_dev_id(dev);
+ const char *igd_type = "Unknown";
+
+ while (igd_info_table != NULL) {
+ if (igd_info_table[i].igdid == igdid) {
+ igd_type = igd_info_table[i].name;
+ break;
+ }
+ i++;
+ igd_info_table++;
+ }
+ printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
+ igdid, get_dev_revision(dev), igd_type);
+}
+
+void report_platform_info(void)
+{
+ struct cpu_info* cpu_info_table = soc_get_cpu_table();
+ struct mch_info* mch_info_table = soc_get_mch_table();
+ struct pch_info* pch_info_table = soc_get_pch_table();
+ struct igd_info* igd_info_table = soc_get_igd_table();
+
+ if (cpu_info_table != NULL)
+ report_cpu_info(cpu_info_table);
+
+ if (mch_info_table != NULL)
+ report_mch_info(mch_info_table);
+
+ if (pch_info_table != NULL)
+ report_pch_info(pch_info_table);
+
+ if (igd_info_table != NULL)
+ report_igd_info(igd_info_table);
+}
diff --git a/src/soc/intel/common/basecode/include/intelbasecode/report_platform.h b/src/soc/intel/common/basecode/include/intelbasecode/report_platform.h
new file mode 100644
index 0000000..a1f1bea
--- /dev/null
+++ b/src/soc/intel/common/basecode/include/intelbasecode/report_platform.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BASECODE_REPORT_PLATFORM_H
+#define SOC_INTEL_COMMON_BASECODE_REPORT_PLATFORM_H
+
+struct cpu_info{
+ u32 cpuid;
+ const char *name;
+};
+
+struct mch_info{
+ u16 mchid;
+ const char *name;
+};
+
+struct pch_info{
+ u16 lpcid;
+ const char *name;
+};
+
+struct igd_info{
+ u16 igdid;
+ const char *name;
+};
+
+/* SoC call to get a pointer to cpu_info table/array */
+struct cpu_info* soc_get_cpu_structure(void);
+
+/* SoC call to get a pointer to mch_info table/array */
+struct mch_info* soc_get_mch_structure(void);
+
+/* SoC call to get a pointer to pch_info table/array */
+struct pch_info* soc_get_pch_structure(void);
+
+/* SoC call to get a pointer to igd_info table/array */
+struct igd_info* soc_get_igd_structure(void);
+
+/* Report CPU, PCH, MCH, IGD information during boot time */
+void report_platform_info(void);
+
+#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id1497b72f784db00a334544f6c5ddc2774049107
Gerrit-Change-Number: 25810
Gerrit-PatchSet: 1
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
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