<p>Bora Guvendik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25810">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]soc/intel/common: Add common code to report platform information<br><br>Add common code so that all SoC can display CPU, MCH, PCH and<br>IGD information if SoC provides the necessary tables.<br><br>Change-Id: Id1497b72f784db00a334544f6c5ddc2774049107<br>Signed-off-by: Bora Guvendik <bora.guvendik@intel.com><br>---<br>M src/soc/intel/common/basecode/bootblock/Kconfig<br>M src/soc/intel/common/basecode/bootblock/Makefile.inc<br>M src/soc/intel/common/basecode/bootblock/bootblock.c<br>A src/soc/intel/common/basecode/bootblock/report_platform.c<br>A src/soc/intel/common/basecode/include/intelbasecode/report_platform.h<br>5 files changed, 269 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/25810/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/basecode/bootblock/Kconfig b/src/soc/intel/common/basecode/bootblock/Kconfig</span><br><span>index 754f4a3..2f22550 100644</span><br><span>--- a/src/soc/intel/common/basecode/bootblock/Kconfig</span><br><span>+++ b/src/soc/intel/common/basecode/bootblock/Kconfig</span><br><span>@@ -10,4 +10,10 @@</span><br><span> def_bool y</span><br><span> select SOC_INTEL_COMMON_BLOCK_SA</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config BOOTBLOCK_REPORT_PLATFORM_INFO</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Report CPU, MCH, PCH, IGD information during boot</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/soc/intel/common/basecode/bootblock/Makefile.inc b/src/soc/intel/common/basecode/bootblock/Makefile.inc</span><br><span>index 854196a..ae9ee48 100644</span><br><span>--- a/src/soc/intel/common/basecode/bootblock/Makefile.inc</span><br><span>+++ b/src/soc/intel/common/basecode/bootblock/Makefile.inc</span><br><span>@@ -1 +1,2 @@</span><br><span> bootblock-$(CONFIG_SOC_INTEL_COMMON_BASECODE_BOOTBLOCK) += bootblock.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(BOOTBLOCK_REPORT_PLATFORM_INFO) += report_platform.c</span><br><span>diff --git a/src/soc/intel/common/basecode/bootblock/bootblock.c b/src/soc/intel/common/basecode/bootblock/bootblock.c</span><br><span>index 3ccf9e8..184051b 100644</span><br><span>--- a/src/soc/intel/common/basecode/bootblock/bootblock.c</span><br><span>+++ b/src/soc/intel/common/basecode/bootblock/bootblock.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include <bootblock_common.h></span><br><span> #include <intelbasecode/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/report_platform.h></span><br><span> #include <soc/pch.h></span><br><span> </span><br><span> /*</span><br><span>@@ -60,6 +61,10 @@</span><br><span> </span><br><span> void bootblock_soc_init(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get Platform details - SA, PCH, MCH, CPU etc */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_BOOTBLOCK_REPORT_PLATFORM_INFO))</span><br><span style="color: hsl(120, 100%, 40%);">+ report_platform_info();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> bootblock_cpu_init();</span><br><span> </span><br><span> bootblock_pch_init();</span><br><span>diff --git a/src/soc/intel/common/basecode/bootblock/report_platform.c b/src/soc/intel/common/basecode/bootblock/report_platform.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d6fd7c9</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/basecode/bootblock/report_platform.c</span><br><span>@@ -0,0 +1,203 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015-2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/repot_platfom.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/mp_init.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/bootblock.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define BIOS_SIGN_ID 0x8B</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__attribute__((weak)) struct cpu_info* soc_get_cpu_table(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* return NULL for this dummy API */</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__attribute__((weak)) struct mch_info* soc_get_mch_table(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* return NULL for this dummy API */</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__attribute__((weak)) struct pch_info* soc_get_pch_table(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* return NULL for this dummy API */</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__attribute__((weak)) struct igd_info* soc_get_igd_table(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* return NULL for this dummy API */</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t get_dev_revision(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return pci_read_config8(dev, PCI_REVISION_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint16_t get_dev_id(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return pci_read_config16(dev, PCI_DEVICE_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void report_cpu_info(struct cpu_info* cpu_info_table)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cpuid_result cpuidr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 i, index, t = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */</span><br><span style="color: hsl(120, 100%, 40%);">+ int vt, txt, aes;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t microcode_ver;</span><br><span style="color: hsl(120, 100%, 40%);">+ static const char * const mode[] = {"NOT ", ""};</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *cpu_type = "Unknown";</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 p[13];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ index = 0x80000000;</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuidr = cpuid(index);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cpuidr.eax < 0x80000004) {</span><br><span style="color: hsl(120, 100%, 40%);">+ strcpy(cpu_string, "Platform info not available");</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ int j=0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 2; i <= 4; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuidr = cpuid(index + i);</span><br><span style="color: hsl(120, 100%, 40%);">+ p[j++] = cpuidr.eax;</span><br><span style="color: hsl(120, 100%, 40%);">+ p[j++] = cpuidr.ebx;</span><br><span style="color: hsl(120, 100%, 40%);">+ p[j++] = cpuidr.ecx;</span><br><span style="color: hsl(120, 100%, 40%);">+ p[j++] = cpuidr.edx;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ p[12]=0;</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_name = (char *)p;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Skip leading spaces in CPU name string */</span><br><span style="color: hsl(120, 100%, 40%);">+ while (cpu_name[0] == ' ')</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_name++;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ microcode_ver.lo = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ microcode_ver.hi = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(BIOS_SIGN_ID, microcode_ver);</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuidr = cpuid(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ microcode_ver = rdmsr(BIOS_SIGN_ID);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Look for string to match the name */</span><br><span style="color: hsl(120, 100%, 40%);">+ while (cpu_info_table != NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cpu_info_table[t].cpuid == cpuidr.eax) {</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_type = cpu_info_table[t].name;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ t++;</span><br><span style="color: hsl(120, 100%, 40%);">+ cpu_info_table++;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuidr.eax, cpu_type, microcode_ver.hi);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ mode[aes], mode[txt], mode[vt]);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void report_mch_info(struct mch_info* mch_info_table)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ device_t dev = SA_DEV_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t mchid = get_dev_id(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t mch_revision = get_dev_revision(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *mch_type = "Unknown";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ while (mch_info_table != NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (mch_info_table[i].mchid == mchid) {</span><br><span style="color: hsl(120, 100%, 40%);">+ mch_type = mch_info_table[i].name;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ i++;</span><br><span style="color: hsl(120, 100%, 40%);">+ mch_info_table++;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ mchid, mch_revision, mch_type);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void report_pch_info(struct pch_info* pch_info_table)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ device_t dev = PCH_DEV_LPC;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t lpcid = get_dev_id(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *pch_type = "Unknown";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ while (pch_info_table != NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pch_info_table[i].lpcid == lpcid) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_type = pch_info_table[i].name;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ i++;</span><br><span style="color: hsl(120, 100%, 40%);">+ pch_info_table++;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ lpcid, get_dev_revision(dev), pch_type);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void report_igd_info(struct igd_info* igd_info_table)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ device_t dev = SA_DEV_IGD;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t igdid = get_dev_id(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *igd_type = "Unknown";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ while (igd_info_table != NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (igd_info_table[i].igdid == igdid) {</span><br><span style="color: hsl(120, 100%, 40%);">+ igd_type = igd_info_table[i].name;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ i++;</span><br><span style="color: hsl(120, 100%, 40%);">+ igd_info_table++;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ igdid, get_dev_revision(dev), igd_type);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void report_platform_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cpu_info* cpu_info_table = soc_get_cpu_table();</span><br><span style="color: hsl(120, 100%, 40%);">+ struct mch_info* mch_info_table = soc_get_mch_table();</span><br><span style="color: hsl(120, 100%, 40%);">+ struct pch_info* pch_info_table = soc_get_pch_table();</span><br><span style="color: hsl(120, 100%, 40%);">+ struct igd_info* igd_info_table = soc_get_igd_table();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (cpu_info_table != NULL)</span><br><span style="color: hsl(120, 100%, 40%);">+ report_cpu_info(cpu_info_table);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (mch_info_table != NULL)</span><br><span style="color: hsl(120, 100%, 40%);">+ report_mch_info(mch_info_table);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pch_info_table != NULL)</span><br><span style="color: hsl(120, 100%, 40%);">+ report_pch_info(pch_info_table);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (igd_info_table != NULL)</span><br><span style="color: hsl(120, 100%, 40%);">+ report_igd_info(igd_info_table);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/common/basecode/include/intelbasecode/report_platform.h b/src/soc/intel/common/basecode/include/intelbasecode/report_platform.h</span><br><span>new file mode 100644</span><br><span>index 0000000..a1f1bea</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/basecode/include/intelbasecode/report_platform.h</span><br><span>@@ -0,0 +1,54 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_INTEL_COMMON_BASECODE_REPORT_PLATFORM_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_INTEL_COMMON_BASECODE_REPORT_PLATFORM_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct cpu_info{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 cpuid;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *name;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct mch_info{</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 mchid;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *name;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct pch_info{</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 lpcid;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *name;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct igd_info{</span><br><span style="color: hsl(120, 100%, 40%);">+ u16 igdid;</span><br><span style="color: hsl(120, 100%, 40%);">+ const char *name;</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SoC call to get a pointer to cpu_info table/array */</span><br><span style="color: hsl(120, 100%, 40%);">+struct cpu_info* soc_get_cpu_structure(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SoC call to get a pointer to mch_info table/array */</span><br><span style="color: hsl(120, 100%, 40%);">+struct mch_info* soc_get_mch_structure(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SoC call to get a pointer to pch_info table/array */</span><br><span style="color: hsl(120, 100%, 40%);">+struct pch_info* soc_get_pch_structure(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SoC call to get a pointer to igd_info table/array */</span><br><span style="color: hsl(120, 100%, 40%);">+struct igd_info* soc_get_igd_structure(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Report CPU, PCH, MCH, IGD information during boot time */</span><br><span style="color: hsl(120, 100%, 40%);">+void report_platform_info(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25810">change 25810</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25810"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id1497b72f784db00a334544f6c5ddc2774049107 </div>
<div style="display:none"> Gerrit-Change-Number: 25810 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Bora Guvendik <bora.guvendik@intel.com> </div>