[coreboot-gerrit] Change in coreboot[master]: vx900: Move to EARLY_CBMEM_INIT
Lubomir Rintel (Code Review)
gerrit at coreboot.org
Mon Apr 23 23:34:24 CEST 2018
Lubomir Rintel has uploaded this change for review. ( https://review.coreboot.org/25798
Change subject: vx900: Move to EARLY_CBMEM_INIT
......................................................................
vx900: Move to EARLY_CBMEM_INIT
To calculate the CBMEM address we need to determine the framebuffer
size early in the ROMSTAGE. The framebuffer size is then cached in the
chipset scratch pad.
Caching the size in a CAR_GLOBAL doesn't seem possible since
car_get_var() would eventually recurse back to cbmem_top().
Calculating the size each time cbmem_top() is called would be possible,
but we'd loose some logging that seems useful, since printk() would
recurse to cbmem_top() too with CONSOLE_CBMEM enabled.
Change-Id: Ib9ae0f97f9f769a20a610f8d76f14165fb924042
Signed-off-by: Lubomir Rintel <lkundrak at v3.sk>
---
M src/mainboard/via/epia-m850/romstage.c
M src/northbridge/via/vx900/Kconfig
M src/northbridge/via/vx900/Makefile.inc
M src/northbridge/via/vx900/chrome9hd.c
A src/northbridge/via/vx900/memmap.c
M src/northbridge/via/vx900/northbridge.c
M src/northbridge/via/vx900/raminit_ddr3.c
M src/northbridge/via/vx900/vx900.h
8 files changed, 129 insertions(+), 96 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/25798/1
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
index f16b9b0..1b7568d 100644
--- a/src/mainboard/via/epia-m850/romstage.c
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -80,7 +80,7 @@
ram_check((1 << 24), 0x80);
ram_check((512 + 256 - 1) << 20, 0x80);
ram_check(0x80c0000, 0x80);
- tolm = ((pci_read_config16(MCU, 0x84) & 0xfff0) >> 4) << 20;
+ tolm = vx900_get_tolm () << 20;
if (tolm > (1 * (u32) GiB))
ram_check(1024 << 10, 0x80);
if (tolm > (2 * (u32) GiB))
@@ -88,6 +88,10 @@
printk(BIOS_DEBUG, "We passed RAM verify\n");
+ /* FIXME: read fb_size from CMOS, but until that is implemented, start
+ * from 512MB */
+ vx900_set_chrome9hd_fb_size (512);
+
/* We got RAM working, now we can write the timestamps to RAM */
#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)
cbmem_recovery(0);
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index bb5e06f..e9d9451 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -21,7 +21,6 @@
select HAVE_DEBUG_RAM_SETUP
select HAVE_DEBUG_SMBUS
select HAVE_HARD_RESET
- select LATE_CBMEM_INIT
if NORTHBRIDGE_VIA_VX900
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index b46f880..bbfe63b 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -21,6 +21,7 @@
romstage-y += early_vx900.c
romstage-y += early_host_bus_ctl.c
romstage-y += raminit_ddr3.c
+romstage-y += memmap.c
romstage-y += ./../../../device/dram/ddr3.c
romstage-y += ./../../../southbridge/via/common/early_smbus_delay.c
romstage-y += ./../../../southbridge/via/common/early_smbus_is_busy.c
@@ -36,6 +37,7 @@
ramstage-y += traf_ctrl.c
ramstage-y += sata.c
ramstage-y += lpc.c
+ramstage-y += memmap.c
# The buildsystem only includes this file if CONFIG_VGA is selected.
# We need to do some VGA I/O before the VGA can be initialized. We can make good
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c
index 147b308..d8c3b1e 100644
--- a/src/northbridge/via/vx900/chrome9hd.c
+++ b/src/northbridge/via/vx900/chrome9hd.c
@@ -23,9 +23,6 @@
#include "vx900.h"
-#define CHROME_9_HD_MIN_FB_SIZE 8
-#define CHROME_9_HD_MAX_FB_SIZE 512
-
/**
* @file chrome9hd.c
*
@@ -60,77 +57,6 @@
* useful considering we only have 8GB (33 bits) of memory-mapped space.
*/
-/* Helper to determine the framebuffer size */
-u32 chrome9hd_fb_size(void)
-{
- static u32 fb_size = 0;
- u8 reg8, ranksize;
- u32 size_mb, tom_mb, max_size_mb;
- int i;
- /* We do some PCI and CMOS IO to find our value, so if we've already
- * found it, save some time */
- if (fb_size != 0)
- return fb_size;
- /* FIXME: read fb_size from CMOS, but until that is implemented, start
- * from 512MB */
- size_mb = 512;
-
- /* The minimum framebuffer size is 8MB. */
- size_mb = MAX(size_mb, CHROME_9_HD_MIN_FB_SIZE);
-
- const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VX900_MEMCTRL,
- 0);
- /*
- * We have two limitations on the maximum framebuffer size:
- * 1) (Sanity) No more that 1/4 of system RAM
- * 2) (Hardware limitation) No larger than DRAM in last rank
- * Check both of these limitations and apply them to our framebuffer */
- tom_mb = (pci_read_config16(mcu, 0x88) & 0x07ff) << (24 - 20);
- max_size_mb = tom_mb >> 2;
- if (size_mb > max_size_mb) {
- printk(BIOS_ALERT, "The framebuffer size of %dMB is larger"
- " than 1/4 of available memory.\n"
- " Limiting framebuffer to %dMB\n", size_mb, max_size_mb);
- size_mb = max_size_mb;
- }
-
- /* Now handle limitation #2
- * Look at the ending address of the memory ranks, from last to first,
- * until we find one that is not zero. That is our last rank, and its
- * size is the limit of our framebuffer. */
- /* FIXME: This has a bug. If we remap memory above 4G, we consider the
- * memory hole as part of our RAM. Thus if we install 3G, with a TOLM of
- * 2.5G, our TOM will be at 5G and we'll assume we have 5G RAM instead
- * of the actual 3.5G */
- for (i = VX900_MAX_MEM_RANKS - 1; i > -1; i--) {
- reg8 = pci_read_config8(mcu, 0x40 + i);
- if (reg8 == 0)
- continue;
- /* We've reached the last populated rank */
- ranksize = reg8 - pci_read_config8(mcu, 0x48 + i);
- max_size_mb = ranksize << 6;
- /* That's it. We got what we needed. */
- break;
- };
- if (size_mb > max_size_mb) {
- printk(BIOS_ALERT, "The framebuffer size of %dMB is larger"
- " than size of the last DRAM rank.\n"
- " Limiting framebuffer to %dMB\n", size_mb, max_size_mb);
- size_mb = max_size_mb;
- }
-
- /* Now round the framebuffer size to the closest power of 2 */
- u8 fb_pow = 0;
- while (size_mb >> fb_pow)
- fb_pow++;
- fb_pow--;
- size_mb = (1 << fb_pow);
- /* We store the framebuffer size in bytes, for simplicity */
- fb_size = size_mb << 20;
- return fb_size;
-}
-
/**
* vx900_int15
*
@@ -214,7 +140,7 @@
static void chrome9hd_handle_uma(device_t dev)
{
/* Mirror mirror, shiny glass, tell me that is not my ass */
- u32 fb_size = chrome9hd_fb_size() >> 20;
+ u32 fb_size = vx900_get_chrome9hd_fb_size() >> 20;
u8 fb_pow = 0;
while (fb_size >> fb_pow)
diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c
new file mode 100644
index 0000000..1b28f48
--- /dev/null
+++ b/src/northbridge/via/vx900/memmap.c
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me at gmail.com>
+ * Copyright (C) 2018 Lubomir Rintel <lkundrak at v3.sk>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define __SIMPLE_DEVICE__
+
+#include "vx900.h"
+
+#include <device/pci.h>
+#include <cbmem.h>
+
+#define MCU PCI_DEV(0, 0, 3)
+#define SCRATCH PCI_DEV(0, 0, 6)
+
+#define CHROME_9_HD_MIN_FB_SIZE 8
+#define CHROME_9_HD_MAX_FB_SIZE 512
+
+/* Helper to determine the framebuffer size */
+void vx900_set_chrome9hd_fb_size(u32 size_mb)
+{
+ u8 reg8, ranksize;
+ u32 tom_mb, max_size_mb;
+ int i;
+
+ /* The minimum framebuffer size is 8MB. */
+ size_mb = MAX(size_mb, CHROME_9_HD_MIN_FB_SIZE);
+
+ /*
+ * We have two limitations on the maximum framebuffer size:
+ * 1) (Sanity) No more that 1/4 of system RAM
+ * 2) (Hardware limitation) No larger than DRAM in last rank
+ * Check both of these limitations and apply them to our framebuffer */
+ tom_mb = (pci_read_config16(MCU, 0x88) & 0x07ff) << (24 - 20);
+ max_size_mb = tom_mb >> 2;
+ if (size_mb > max_size_mb) {
+ printk(BIOS_ALERT, "The framebuffer size of %dMB is larger"
+ " than 1/4 of available memory.\n"
+ " Limiting framebuffer to %dMB\n", size_mb, max_size_mb);
+ size_mb = max_size_mb;
+ }
+
+ /* Now handle limitation #2
+ * Look at the ending address of the memory ranks, from last to first,
+ * until we find one that is not zero. That is our last rank, and its
+ * size is the limit of our framebuffer. */
+ /* FIXME: This has a bug. If we remap memory above 4G, we consider the
+ * memory hole as part of our RAM. Thus if we install 3G, with a TOLM of
+ * 2.5G, our TOM will be at 5G and we'll assume we have 5G RAM instead
+ * of the actual 3.5G */
+ for (i = VX900_MAX_MEM_RANKS - 1; i > -1; i--) {
+ reg8 = pci_read_config8(MCU, 0x40 + i);
+ if (reg8 == 0)
+ continue;
+ /* We've reached the last populated rank */
+ ranksize = reg8 - pci_read_config8(MCU, 0x48 + i);
+ max_size_mb = ranksize << 6;
+ /* That's it. We got what we needed. */
+ break;
+ };
+ if (size_mb > max_size_mb) {
+ printk(BIOS_ALERT, "The framebuffer size of %dMB is larger"
+ " than size of the last DRAM rank.\n"
+ " Limiting framebuffer to %dMB\n", size_mb, max_size_mb);
+ size_mb = max_size_mb;
+ }
+
+ /* Now round the framebuffer size to the closest power of 2 */
+ u8 fb_pow = 0;
+ while (size_mb >> fb_pow)
+ fb_pow++;
+ fb_pow--;
+ size_mb = (1 << fb_pow);
+
+ /* We store the framebuffer size in bytes, for simplicity */
+ pci_write_config32(SCRATCH, 0x40, size_mb << 20);
+}
+
+u32 vx900_get_chrome9hd_fb_size(void)
+{
+ return pci_read_config32(SCRATCH, 0x40);
+}
+
+u32 vx900_get_tolm(void)
+{
+ return (pci_read_config16(MCU, 0x84) & 0xfff0) >> 4;
+}
+
+void *cbmem_top(void)
+{
+ u32 tolm;
+
+ tolm = vx900_get_tolm ();
+
+ if (tolm > 0xfc0 || tolm <= 0x3ff)
+ return NULL;
+
+ return (void *)((tolm << 20) - (vx900_get_chrome9hd_fb_size ()));
+}
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index 774f744..fc95b24 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -216,7 +216,7 @@
static void vx900_set_resources(device_t dev)
{
- u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk;
+ u32 tomk, full_tolmk, fbufk, tolmk;
printk(BIOS_DEBUG, "========================================"
"========================================\n");
@@ -235,25 +235,18 @@
"but couldn't find it. Halting.\n");
}
- /* How much low adrress space do we have? */
- pci_tolm = find_pci_tolm(dev->link_list);
- printk(BIOS_SPEW, "Found PCI tolm at %.8x\n", pci_tolm);
- printk(BIOS_SPEW, "Found PCI tolm at %dMB\n", pci_tolm >> 20);
-
/* Figure out the total amount of RAM */
tomk = vx900_get_top_of_ram(mcu) >> 10;
printk(BIOS_SPEW, "Found top of memory at %dMB\n", tomk >> 10);
/* Do the same for top of low RAM */
- vx900_tolm = (pci_read_config16(mcu, 0x84) & 0xfff0) >> 4;
- full_tolmk = vx900_tolm << (20 - 10);
+ full_tolmk = vx900_get_tolm() << (20 - 10);
/* Remap above 4G if needed */
- full_tolmk = MIN(full_tolmk, pci_tolm >> 10);
printk(BIOS_SPEW, "Found top of low memory at %dMB\n",
full_tolmk >> 10);
/* What about the framebuffer for the integrated GPU? */
- fbufk = chrome9hd_fb_size() >> 10;
+ fbufk = vx900_get_chrome9hd_fb_size() >> 10;
printk(BIOS_SPEW, "Integrated graphics buffer: %dMB\n", fbufk >> 10);
/* Can't use the framebuffer as system RAM, sorry */
@@ -275,12 +268,11 @@
printk(BIOS_DEBUG, "UMA @ %lldMB + %lldMB\n", uma_memory_base >> 20,
uma_memory_size >> 20);
/* FIXME: How do we handle remapping above 4G? */
- u64 tor = vx900_remap_above_4g(mcu, pci_tolm);
+
+ u64 tor = vx900_remap_above_4g(mcu, full_tolmk << 10);
if (tor)
ram_resource(dev, idx++, RAM_4GB >> 10, (tor - RAM_4GB) >> 10);
- set_late_cbmem_top(tolmk << 10);
-
printk(BIOS_DEBUG, "======================================================\n");
assign_resources(dev->link_list);
}
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index eec4aa3..d0914e5 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -1492,7 +1492,6 @@
size_t i, vrank = 0;
u8 reg8;
u32 ramsize_mb = 0, tolm_mb;
- const u32 TOLM_3_5G = (7 << 29);
/* All unused physical ranks go to VR3. Otherwise, the MCU might be
* trying to read or write from unused ranks, or even worse, write some
* bits to the rank we want, and some to the unused ranks, even though
@@ -1534,10 +1533,8 @@
vrank++;
}
- /* Limit the Top of Low memory at 3.5G
- * Not to worry, we'll set tolm in ramstage, once we have initialized
- * all devices and know pci_tolm. */
- tolm_mb = MIN(ramsize_mb, TOLM_3_5G >> 20);
+ /* Limit the Top of Low memory at PCI MMCONF window (3.5G) */
+ tolm_mb = MIN(ramsize_mb, CONFIG_MMCONF_BASE_ADDRESS >> 20);
u16 reg_tolm = (tolm_mb << 4) & 0xfff0;
pci_mod_config16(MCU, 0x84, 0xfff0, reg_tolm);
diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h
index 216f637..fd60f4f 100644
--- a/src/northbridge/via/vx900/vx900.h
+++ b/src/northbridge/via/vx900/vx900.h
@@ -37,7 +37,9 @@
#include <console/console.h>
-u32 chrome9hd_fb_size(void);
+u32 vx900_get_tolm(void);
+void vx900_set_chrome9hd_fb_size(u32 size_mb);
+u32 vx900_get_chrome9hd_fb_size(void);
u8 vx900_int15_get_5f18_bl(void);
uint64_t get_uma_memory_base(void);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib9ae0f97f9f769a20a610f8d76f14165fb924042
Gerrit-Change-Number: 25798
Gerrit-PatchSet: 1
Gerrit-Owner: Lubomir Rintel <lkundrak at v3.sk>
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