<p>Lubomir Rintel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25798">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vx900: Move to EARLY_CBMEM_INIT<br><br>To calculate the CBMEM address we need to determine the framebuffer<br>size early in the ROMSTAGE. The framebuffer size is then cached in the<br>chipset scratch pad.<br><br>Caching the size in a CAR_GLOBAL doesn't seem possible since<br>car_get_var() would eventually recurse back to cbmem_top().<br><br>Calculating the size each time cbmem_top() is called would be possible,<br>but we'd loose some logging that seems useful, since printk() would<br>recurse to cbmem_top() too with CONSOLE_CBMEM enabled.<br><br>Change-Id: Ib9ae0f97f9f769a20a610f8d76f14165fb924042<br>Signed-off-by: Lubomir Rintel <lkundrak@v3.sk><br>---<br>M src/mainboard/via/epia-m850/romstage.c<br>M src/northbridge/via/vx900/Kconfig<br>M src/northbridge/via/vx900/Makefile.inc<br>M src/northbridge/via/vx900/chrome9hd.c<br>A src/northbridge/via/vx900/memmap.c<br>M src/northbridge/via/vx900/northbridge.c<br>M src/northbridge/via/vx900/raminit_ddr3.c<br>M src/northbridge/via/vx900/vx900.h<br>8 files changed, 129 insertions(+), 96 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/25798/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c</span><br><span>index f16b9b0..1b7568d 100644</span><br><span>--- a/src/mainboard/via/epia-m850/romstage.c</span><br><span>+++ b/src/mainboard/via/epia-m850/romstage.c</span><br><span>@@ -80,7 +80,7 @@</span><br><span> ram_check((1 << 24), 0x80);</span><br><span> ram_check((512 + 256 - 1) << 20, 0x80);</span><br><span> ram_check(0x80c0000, 0x80);</span><br><span style="color: hsl(0, 100%, 40%);">- tolm = ((pci_read_config16(MCU, 0x84) & 0xfff0) >> 4) << 20;</span><br><span style="color: hsl(120, 100%, 40%);">+ tolm = vx900_get_tolm () << 20;</span><br><span> if (tolm > (1 * (u32) GiB))</span><br><span> ram_check(1024 << 10, 0x80);</span><br><span> if (tolm > (2 * (u32) GiB))</span><br><span>@@ -88,6 +88,10 @@</span><br><span> </span><br><span> printk(BIOS_DEBUG, "We passed RAM verify\n");</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* FIXME: read fb_size from CMOS, but until that is implemented, start</span><br><span style="color: hsl(120, 100%, 40%);">+ * from 512MB */</span><br><span style="color: hsl(120, 100%, 40%);">+ vx900_set_chrome9hd_fb_size (512);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* We got RAM working, now we can write the timestamps to RAM */</span><br><span> #if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)</span><br><span> cbmem_recovery(0);</span><br><span>diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig</span><br><span>index bb5e06f..e9d9451 100644</span><br><span>--- a/src/northbridge/via/vx900/Kconfig</span><br><span>+++ b/src/northbridge/via/vx900/Kconfig</span><br><span>@@ -21,7 +21,6 @@</span><br><span> select HAVE_DEBUG_RAM_SETUP</span><br><span> select HAVE_DEBUG_SMBUS</span><br><span> select HAVE_HARD_RESET</span><br><span style="color: hsl(0, 100%, 40%);">- select LATE_CBMEM_INIT</span><br><span> </span><br><span> if NORTHBRIDGE_VIA_VX900</span><br><span> </span><br><span>diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc</span><br><span>index b46f880..bbfe63b 100644</span><br><span>--- a/src/northbridge/via/vx900/Makefile.inc</span><br><span>+++ b/src/northbridge/via/vx900/Makefile.inc</span><br><span>@@ -21,6 +21,7 @@</span><br><span> romstage-y += early_vx900.c</span><br><span> romstage-y += early_host_bus_ctl.c</span><br><span> romstage-y += raminit_ddr3.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += memmap.c</span><br><span> romstage-y += ./../../../device/dram/ddr3.c</span><br><span> romstage-y += ./../../../southbridge/via/common/early_smbus_delay.c</span><br><span> romstage-y += ./../../../southbridge/via/common/early_smbus_is_busy.c</span><br><span>@@ -36,6 +37,7 @@</span><br><span> ramstage-y += traf_ctrl.c</span><br><span> ramstage-y += sata.c</span><br><span> ramstage-y += lpc.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += memmap.c</span><br><span> </span><br><span> # The buildsystem only includes this file if CONFIG_VGA is selected.</span><br><span> # We need to do some VGA I/O before the VGA can be initialized. We can make good</span><br><span>diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c</span><br><span>index 147b308..d8c3b1e 100644</span><br><span>--- a/src/northbridge/via/vx900/chrome9hd.c</span><br><span>+++ b/src/northbridge/via/vx900/chrome9hd.c</span><br><span>@@ -23,9 +23,6 @@</span><br><span> </span><br><span> #include "vx900.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define CHROME_9_HD_MIN_FB_SIZE 8</span><br><span style="color: hsl(0, 100%, 40%);">-#define CHROME_9_HD_MAX_FB_SIZE 512</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /**</span><br><span> * @file chrome9hd.c</span><br><span> *</span><br><span>@@ -60,77 +57,6 @@</span><br><span> * useful considering we only have 8GB (33 bits) of memory-mapped space.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Helper to determine the framebuffer size */</span><br><span style="color: hsl(0, 100%, 40%);">-u32 chrome9hd_fb_size(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- static u32 fb_size = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8, ranksize;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 size_mb, tom_mb, max_size_mb;</span><br><span style="color: hsl(0, 100%, 40%);">- int i;</span><br><span style="color: hsl(0, 100%, 40%);">- /* We do some PCI and CMOS IO to find our value, so if we've already</span><br><span style="color: hsl(0, 100%, 40%);">- * found it, save some time */</span><br><span style="color: hsl(0, 100%, 40%);">- if (fb_size != 0)</span><br><span style="color: hsl(0, 100%, 40%);">- return fb_size;</span><br><span style="color: hsl(0, 100%, 40%);">- /* FIXME: read fb_size from CMOS, but until that is implemented, start</span><br><span style="color: hsl(0, 100%, 40%);">- * from 512MB */</span><br><span style="color: hsl(0, 100%, 40%);">- size_mb = 512;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* The minimum framebuffer size is 8MB. */</span><br><span style="color: hsl(0, 100%, 40%);">- size_mb = MAX(size_mb, CHROME_9_HD_MIN_FB_SIZE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,</span><br><span style="color: hsl(0, 100%, 40%);">- PCI_DEVICE_ID_VIA_VX900_MEMCTRL,</span><br><span style="color: hsl(0, 100%, 40%);">- 0);</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * We have two limitations on the maximum framebuffer size:</span><br><span style="color: hsl(0, 100%, 40%);">- * 1) (Sanity) No more that 1/4 of system RAM</span><br><span style="color: hsl(0, 100%, 40%);">- * 2) (Hardware limitation) No larger than DRAM in last rank</span><br><span style="color: hsl(0, 100%, 40%);">- * Check both of these limitations and apply them to our framebuffer */</span><br><span style="color: hsl(0, 100%, 40%);">- tom_mb = (pci_read_config16(mcu, 0x88) & 0x07ff) << (24 - 20);</span><br><span style="color: hsl(0, 100%, 40%);">- max_size_mb = tom_mb >> 2;</span><br><span style="color: hsl(0, 100%, 40%);">- if (size_mb > max_size_mb) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ALERT, "The framebuffer size of %dMB is larger"</span><br><span style="color: hsl(0, 100%, 40%);">- " than 1/4 of available memory.\n"</span><br><span style="color: hsl(0, 100%, 40%);">- " Limiting framebuffer to %dMB\n", size_mb, max_size_mb);</span><br><span style="color: hsl(0, 100%, 40%);">- size_mb = max_size_mb;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Now handle limitation #2</span><br><span style="color: hsl(0, 100%, 40%);">- * Look at the ending address of the memory ranks, from last to first,</span><br><span style="color: hsl(0, 100%, 40%);">- * until we find one that is not zero. That is our last rank, and its</span><br><span style="color: hsl(0, 100%, 40%);">- * size is the limit of our framebuffer. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* FIXME: This has a bug. If we remap memory above 4G, we consider the</span><br><span style="color: hsl(0, 100%, 40%);">- * memory hole as part of our RAM. Thus if we install 3G, with a TOLM of</span><br><span style="color: hsl(0, 100%, 40%);">- * 2.5G, our TOM will be at 5G and we'll assume we have 5G RAM instead</span><br><span style="color: hsl(0, 100%, 40%);">- * of the actual 3.5G */</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = VX900_MAX_MEM_RANKS - 1; i > -1; i--) {</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(mcu, 0x40 + i);</span><br><span style="color: hsl(0, 100%, 40%);">- if (reg8 == 0)</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">- /* We've reached the last populated rank */</span><br><span style="color: hsl(0, 100%, 40%);">- ranksize = reg8 - pci_read_config8(mcu, 0x48 + i);</span><br><span style="color: hsl(0, 100%, 40%);">- max_size_mb = ranksize << 6;</span><br><span style="color: hsl(0, 100%, 40%);">- /* That's it. We got what we needed. */</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">- if (size_mb > max_size_mb) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ALERT, "The framebuffer size of %dMB is larger"</span><br><span style="color: hsl(0, 100%, 40%);">- " than size of the last DRAM rank.\n"</span><br><span style="color: hsl(0, 100%, 40%);">- " Limiting framebuffer to %dMB\n", size_mb, max_size_mb);</span><br><span style="color: hsl(0, 100%, 40%);">- size_mb = max_size_mb;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Now round the framebuffer size to the closest power of 2 */</span><br><span style="color: hsl(0, 100%, 40%);">- u8 fb_pow = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- while (size_mb >> fb_pow)</span><br><span style="color: hsl(0, 100%, 40%);">- fb_pow++;</span><br><span style="color: hsl(0, 100%, 40%);">- fb_pow--;</span><br><span style="color: hsl(0, 100%, 40%);">- size_mb = (1 << fb_pow);</span><br><span style="color: hsl(0, 100%, 40%);">- /* We store the framebuffer size in bytes, for simplicity */</span><br><span style="color: hsl(0, 100%, 40%);">- fb_size = size_mb << 20;</span><br><span style="color: hsl(0, 100%, 40%);">- return fb_size;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /**</span><br><span> * vx900_int15</span><br><span> *</span><br><span>@@ -214,7 +140,7 @@</span><br><span> static void chrome9hd_handle_uma(device_t dev)</span><br><span> {</span><br><span> /* Mirror mirror, shiny glass, tell me that is not my ass */</span><br><span style="color: hsl(0, 100%, 40%);">- u32 fb_size = chrome9hd_fb_size() >> 20;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 fb_size = vx900_get_chrome9hd_fb_size() >> 20;</span><br><span> </span><br><span> u8 fb_pow = 0;</span><br><span> while (fb_size >> fb_pow)</span><br><span>diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c</span><br><span>new file mode 100644</span><br><span>index 0000000..1b28f48</span><br><span>--- /dev/null</span><br><span>+++ b/src/northbridge/via/vx900/memmap.c</span><br><span>@@ -0,0 +1,111 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Lubomir Rintel <lkundrak@v3.sk></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software: you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation, either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define __SIMPLE_DEVICE__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "vx900.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define MCU PCI_DEV(0, 0, 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SCRATCH PCI_DEV(0, 0, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHROME_9_HD_MIN_FB_SIZE 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define CHROME_9_HD_MAX_FB_SIZE 512</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Helper to determine the framebuffer size */</span><br><span style="color: hsl(120, 100%, 40%);">+void vx900_set_chrome9hd_fb_size(u32 size_mb)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reg8, ranksize;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tom_mb, max_size_mb;</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* The minimum framebuffer size is 8MB. */</span><br><span style="color: hsl(120, 100%, 40%);">+ size_mb = MAX(size_mb, CHROME_9_HD_MIN_FB_SIZE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * We have two limitations on the maximum framebuffer size:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1) (Sanity) No more that 1/4 of system RAM</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2) (Hardware limitation) No larger than DRAM in last rank</span><br><span style="color: hsl(120, 100%, 40%);">+ * Check both of these limitations and apply them to our framebuffer */</span><br><span style="color: hsl(120, 100%, 40%);">+ tom_mb = (pci_read_config16(MCU, 0x88) & 0x07ff) << (24 - 20);</span><br><span style="color: hsl(120, 100%, 40%);">+ max_size_mb = tom_mb >> 2;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (size_mb > max_size_mb) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ALERT, "The framebuffer size of %dMB is larger"</span><br><span style="color: hsl(120, 100%, 40%);">+ " than 1/4 of available memory.\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " Limiting framebuffer to %dMB\n", size_mb, max_size_mb);</span><br><span style="color: hsl(120, 100%, 40%);">+ size_mb = max_size_mb;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Now handle limitation #2</span><br><span style="color: hsl(120, 100%, 40%);">+ * Look at the ending address of the memory ranks, from last to first,</span><br><span style="color: hsl(120, 100%, 40%);">+ * until we find one that is not zero. That is our last rank, and its</span><br><span style="color: hsl(120, 100%, 40%);">+ * size is the limit of our framebuffer. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FIXME: This has a bug. If we remap memory above 4G, we consider the</span><br><span style="color: hsl(120, 100%, 40%);">+ * memory hole as part of our RAM. Thus if we install 3G, with a TOLM of</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2.5G, our TOM will be at 5G and we'll assume we have 5G RAM instead</span><br><span style="color: hsl(120, 100%, 40%);">+ * of the actual 3.5G */</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = VX900_MAX_MEM_RANKS - 1; i > -1; i--) {</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(MCU, 0x40 + i);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (reg8 == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We've reached the last populated rank */</span><br><span style="color: hsl(120, 100%, 40%);">+ ranksize = reg8 - pci_read_config8(MCU, 0x48 + i);</span><br><span style="color: hsl(120, 100%, 40%);">+ max_size_mb = ranksize << 6;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* That's it. We got what we needed. */</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ if (size_mb > max_size_mb) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ALERT, "The framebuffer size of %dMB is larger"</span><br><span style="color: hsl(120, 100%, 40%);">+ " than size of the last DRAM rank.\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " Limiting framebuffer to %dMB\n", size_mb, max_size_mb);</span><br><span style="color: hsl(120, 100%, 40%);">+ size_mb = max_size_mb;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Now round the framebuffer size to the closest power of 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 fb_pow = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ while (size_mb >> fb_pow)</span><br><span style="color: hsl(120, 100%, 40%);">+ fb_pow++;</span><br><span style="color: hsl(120, 100%, 40%);">+ fb_pow--;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_mb = (1 << fb_pow);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We store the framebuffer size in bytes, for simplicity */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SCRATCH, 0x40, size_mb << 20);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u32 vx900_get_chrome9hd_fb_size(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return pci_read_config32(SCRATCH, 0x40);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u32 vx900_get_tolm(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return (pci_read_config16(MCU, 0x84) & 0xfff0) >> 4;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void *cbmem_top(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tolm;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tolm = vx900_get_tolm ();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (tolm > 0xfc0 || tolm <= 0x3ff)</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return (void *)((tolm << 20) - (vx900_get_chrome9hd_fb_size ()));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c</span><br><span>index 774f744..fc95b24 100644</span><br><span>--- a/src/northbridge/via/vx900/northbridge.c</span><br><span>+++ b/src/northbridge/via/vx900/northbridge.c</span><br><span>@@ -216,7 +216,7 @@</span><br><span> </span><br><span> static void vx900_set_resources(device_t dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tomk, full_tolmk, fbufk, tolmk;</span><br><span> </span><br><span> printk(BIOS_DEBUG, "========================================"</span><br><span> "========================================\n");</span><br><span>@@ -235,25 +235,18 @@</span><br><span> "but couldn't find it. Halting.\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* How much low adrress space do we have? */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_tolm = find_pci_tolm(dev->link_list);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "Found PCI tolm at %.8x\n", pci_tolm);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_SPEW, "Found PCI tolm at %dMB\n", pci_tolm >> 20);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Figure out the total amount of RAM */</span><br><span> tomk = vx900_get_top_of_ram(mcu) >> 10;</span><br><span> printk(BIOS_SPEW, "Found top of memory at %dMB\n", tomk >> 10);</span><br><span> </span><br><span> /* Do the same for top of low RAM */</span><br><span style="color: hsl(0, 100%, 40%);">- vx900_tolm = (pci_read_config16(mcu, 0x84) & 0xfff0) >> 4;</span><br><span style="color: hsl(0, 100%, 40%);">- full_tolmk = vx900_tolm << (20 - 10);</span><br><span style="color: hsl(120, 100%, 40%);">+ full_tolmk = vx900_get_tolm() << (20 - 10);</span><br><span> /* Remap above 4G if needed */</span><br><span style="color: hsl(0, 100%, 40%);">- full_tolmk = MIN(full_tolmk, pci_tolm >> 10);</span><br><span> printk(BIOS_SPEW, "Found top of low memory at %dMB\n",</span><br><span> full_tolmk >> 10);</span><br><span> </span><br><span> /* What about the framebuffer for the integrated GPU? */</span><br><span style="color: hsl(0, 100%, 40%);">- fbufk = chrome9hd_fb_size() >> 10;</span><br><span style="color: hsl(120, 100%, 40%);">+ fbufk = vx900_get_chrome9hd_fb_size() >> 10;</span><br><span> printk(BIOS_SPEW, "Integrated graphics buffer: %dMB\n", fbufk >> 10);</span><br><span> </span><br><span> /* Can't use the framebuffer as system RAM, sorry */</span><br><span>@@ -275,12 +268,11 @@</span><br><span> printk(BIOS_DEBUG, "UMA @ %lldMB + %lldMB\n", uma_memory_base >> 20,</span><br><span> uma_memory_size >> 20);</span><br><span> /* FIXME: How do we handle remapping above 4G? */</span><br><span style="color: hsl(0, 100%, 40%);">- u64 tor = vx900_remap_above_4g(mcu, pci_tolm);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ u64 tor = vx900_remap_above_4g(mcu, full_tolmk << 10);</span><br><span> if (tor)</span><br><span> ram_resource(dev, idx++, RAM_4GB >> 10, (tor - RAM_4GB) >> 10);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- set_late_cbmem_top(tolmk << 10);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> printk(BIOS_DEBUG, "======================================================\n");</span><br><span> assign_resources(dev->link_list);</span><br><span> }</span><br><span>diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c</span><br><span>index eec4aa3..d0914e5 100644</span><br><span>--- a/src/northbridge/via/vx900/raminit_ddr3.c</span><br><span>+++ b/src/northbridge/via/vx900/raminit_ddr3.c</span><br><span>@@ -1492,7 +1492,6 @@</span><br><span> size_t i, vrank = 0;</span><br><span> u8 reg8;</span><br><span> u32 ramsize_mb = 0, tolm_mb;</span><br><span style="color: hsl(0, 100%, 40%);">- const u32 TOLM_3_5G = (7 << 29);</span><br><span> /* All unused physical ranks go to VR3. Otherwise, the MCU might be</span><br><span> * trying to read or write from unused ranks, or even worse, write some</span><br><span> * bits to the rank we want, and some to the unused ranks, even though</span><br><span>@@ -1534,10 +1533,8 @@</span><br><span> vrank++;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Limit the Top of Low memory at 3.5G</span><br><span style="color: hsl(0, 100%, 40%);">- * Not to worry, we'll set tolm in ramstage, once we have initialized</span><br><span style="color: hsl(0, 100%, 40%);">- * all devices and know pci_tolm. */</span><br><span style="color: hsl(0, 100%, 40%);">- tolm_mb = MIN(ramsize_mb, TOLM_3_5G >> 20);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Limit the Top of Low memory at PCI MMCONF window (3.5G) */</span><br><span style="color: hsl(120, 100%, 40%);">+ tolm_mb = MIN(ramsize_mb, CONFIG_MMCONF_BASE_ADDRESS >> 20);</span><br><span> u16 reg_tolm = (tolm_mb << 4) & 0xfff0;</span><br><span> pci_mod_config16(MCU, 0x84, 0xfff0, reg_tolm);</span><br><span> </span><br><span>diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h</span><br><span>index 216f637..fd60f4f 100644</span><br><span>--- a/src/northbridge/via/vx900/vx900.h</span><br><span>+++ b/src/northbridge/via/vx900/vx900.h</span><br><span>@@ -37,7 +37,9 @@</span><br><span> </span><br><span> #include <console/console.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-u32 chrome9hd_fb_size(void);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 vx900_get_tolm(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void vx900_set_chrome9hd_fb_size(u32 size_mb);</span><br><span style="color: hsl(120, 100%, 40%);">+u32 vx900_get_chrome9hd_fb_size(void);</span><br><span> u8 vx900_int15_get_5f18_bl(void);</span><br><span> uint64_t get_uma_memory_base(void);</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25798">change 25798</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25798"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib9ae0f97f9f769a20a610f8d76f14165fb924042 </div>
<div style="display:none"> Gerrit-Change-Number: 25798 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lubomir Rintel <lkundrak@v3.sk> </div>