[coreboot-gerrit] Change in coreboot[master]: stoneyridge GPIO: Create and use PAD_INT for interrupt pins
Richard Spiegel (Code Review)
gerrit at coreboot.org
Sat Apr 21 01:50:59 CEST 2018
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25758
Change subject: stoneyridge GPIO: Create and use PAD_INT for interrupt pins
......................................................................
stoneyridge GPIO: Create and use PAD_INT for interrupt pins
The default interrupt control for GPIO pins within stoneyridge is for edge
triggered, high. However, sometimes these need to change, or maybe the
interrupt needs to be reported or delivered. This was the case of platform
grunt, where the interrupt related bits were being changed afterwards.
Ideally all the bits should be programmed through the same procedure.
Create a PAD_INT definition and change function sb_program_gpios() to accept
the output from PAD_INT and program all the necessary bits while keeping
compatibility with other PAD_XX definitions.
BUG=b:72875858
TEST=Add code to report GPIO configuration, build grunt and record a
baseline. Add new code, rebuild grunt and record a test output. Compare
baseline against test, there should be no change in GPIO programming.
Remove code that reports GPIO configuration.
Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/mainboard/google/kahlee/bootblock/bootblock.c
M src/mainboard/google/kahlee/variants/baseboard/gpio.c
M src/soc/amd/stoneyridge/include/soc/gpio.h
M src/soc/amd/stoneyridge/southbridge.c
4 files changed, 80 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/25758/1
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c
index 1eb18f1..9c41d95 100644
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -36,11 +36,4 @@
{
/* Setup TPM decode before verstage */
sb_tpm_decode_spi();
-
- /* Configure cr50 interrupt pin for use in polling tpm status */
- if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) {
- const uint32_t flags = GPIO_EDGEL_TRIG | GPIO_ACTIVE_LOW |
- GPIO_INT_STATUS_EN;
- gpio_set_interrupt(H1_PCH_INT, flags);
- }
}
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 209d5ea..5a93fe3 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -30,16 +30,16 @@
PAD_GPO(GPIO_4, HIGH),
/* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */
- PAD_GPI(GPIO_6, PULL_UP),
+ PAD_INT(GPIO_6, EDGE_HIGH, PULL_UP),
/* GPIO_9 - H1_PCH_INT_ODL, SCI */
- PAD_GPI(GPIO_9, PULL_UP),
+ PAD_INT(GPIO_9, EDGE_LOW_STATUS, PULL_UP),
/* GPIO_15 - EC_IN_RW_OD */
PAD_GPI(GPIO_15, PULL_UP),
/* GPIO_22 - EC_SCI_ODL, SCI */
- PAD_GPI(GPIO_22, PULL_UP),
+ PAD_INT(GPIO_22, EDGE_HIGH, PULL_UP),
/* GPIO_26 - APU_PCIE_RST_L */
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
@@ -80,16 +80,16 @@
PAD_GPO(GPIO_4, HIGH),
/* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */
- PAD_GPI(GPIO_6, PULL_UP),
+ PAD_INT(GPIO_6, EDGE_HIGH, PULL_UP),
/* GPIO_9 - H1_PCH_INT_ODL, SCI */
- PAD_GPI(GPIO_9, PULL_UP),
+ PAD_INT(GPIO_9, EDGE_LOW_STATUS, PULL_UP),
/* GPIO_15 - EC_IN_RW_OD */
PAD_GPI(GPIO_15, PULL_UP),
/* GPIO_22 - EC_SCI_ODL, SCI */
- PAD_GPI(GPIO_22, PULL_UP),
+ PAD_INT(GPIO_22, EDGE_HIGH, PULL_UP),
/* GPIO_24 - EC_PCH_WAKE_L */
PAD_GPI(GPIO_24, PULL_UP),
@@ -142,7 +142,7 @@
PAD_GPI(GPIO_3, PULL_UP),
/* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */
- PAD_GPI(GPIO_5, PULL_UP),
+ PAD_INT(GPIO_5, EDGE_HIGH, PULL_UP),
/* GPIO_7 - APU_PWROK_OD (currently not used) */
PAD_GPI(GPIO_7, PULL_UP),
@@ -154,7 +154,7 @@
PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),
/* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */
- PAD_GPI(GPIO_11, PULL_UP),
+ PAD_INT(GPIO_11, EDGE_HIGH, PULL_UP),
/* GPIO_12 - Unused (TP126) */
PAD_GPI(GPIO_12, PULL_UP),
@@ -163,7 +163,7 @@
PAD_GPI(GPIO_13, PULL_UP),
/* GPIO_14 - APU_HP_INT_ODL, SCI */
- PAD_GPI(GPIO_14, PULL_UP),
+ PAD_INT(GPIO_14, EDGE_HIGH, PULL_UP),
/* GPIO_16 - USB_C0_OC_L */
PAD_NF(GPIO_16, USB_OC0_L, PULL_UP),
@@ -181,7 +181,7 @@
PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),
/* GPIO_21 - APU_PEN_INT_ODL, SCI */
- PAD_GPI(GPIO_21, PULL_UP),
+ PAD_INT(GPIO_21, EDGE_HIGH, PULL_UP),
/* GPIO_24 - USB_A1_OC_ODL */
PAD_NF(GPIO_24, USB_OC3_L, PULL_UP),
@@ -309,7 +309,7 @@
PAD_GPI(GPIO_3, PULL_UP),
/* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */
- PAD_GPI(GPIO_5, PULL_UP),
+ PAD_INT(GPIO_5, EDGE_HIGH, PULL_UP),
/* GPIO_7 - APU_PWROK_OD (currently not used) */
PAD_GPI(GPIO_7, PULL_UP),
@@ -321,7 +321,7 @@
PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),
/* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */
- PAD_GPI(GPIO_11, PULL_UP),
+ PAD_INT(GPIO_11, EDGE_HIGH, PULL_UP),
/* GPIO_12 - EN_PP3300_TRACKPAD */
PAD_GPO(GPIO_12, HIGH),
@@ -330,7 +330,7 @@
PAD_GPI(GPIO_13, PULL_UP),
/* GPIO_14 - APU_HP_INT_ODL, SCI */
- PAD_GPI(GPIO_14, PULL_UP),
+ PAD_INT(GPIO_14, EDGE_HIGH, PULL_UP),
/* GPIO_16 - USB_C0_OC_L */
PAD_NF(GPIO_16, USB_OC0_L, PULL_UP),
@@ -348,7 +348,7 @@
PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),
/* GPIO_21 - APU_PEN_INT_ODL, SCI */
- PAD_GPI(GPIO_21, PULL_UP),
+ PAD_INT(GPIO_21, EDGE_HIGH, PULL_UP),
/* GPIO_25 - SD_CD */
PAD_NF(GPIO_25, SD0_CD, PULL_UP),
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index 0f7ec1b..b408ab2 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -335,6 +335,57 @@
#define GPIO_PULL_PULL_DOWN FCH_GPIO_PULL_DOWN_ENABLE
#define GPIO_PULL_PULL_NONE 0
+/*
+ * Definitions for PAD_INT. It uses the fact that the register bit 16
+ * (bit 0 of control) is the status of the pin(read-only) as a signal
+ * for the code to treat control differently. If bit 0 is set, control
+ * will be interpreted as:
+ * Bit 7 register bit 21 pull down
+ * Bit 6 register bit 20 pull up
+ * Bits 5-1 register bits 12-8 interrupt related bits.
+ */
+#define GPIO_INT_PULL_NONE 0x00
+#define GPIO_INT_PULL_UP 0x40
+#define GPIO_INT_PULL_DOWN 0x80
+#define GPIO_INT_EDGE_HIGH 0x00
+#define GPIO_INT_EDGE_LOW 0x04
+#define GPIO_INT_BOTH_EDGES 0x08
+#define GPIO_INT_LEVEL_HIGH 0x02
+#define GPIO_INT_LEVEL_LOW 0x06
+#define GPIO_INT_EDGE_HIGH 0x00
+#define GPIO_INT_EDGE_LOW 0x04
+#define GPIO_INT_BOTH_EDGES 0x08
+#define GPIO_INT_LEVEL_HIGH 0x02
+#define GPIO_INT_LEVEL_LOW 0x06
+#define GPIO_INT_EDGE_HIGH_STATUS 0x10
+#define GPIO_INT_EDGE_LOW_STATUS 0x14
+#define GPIO_INT_BOTH_EDGES_STATUS 0x18
+#define GPIO_INT_LEVEL_HIGH_STATUS 0x12
+#define GPIO_INT_LEVEL_LOW_STATUS 0x16
+#define GPIO_INT_EDGE_HIGH_DELIVER 0x20
+#define GPIO_INT_EDGE_LOW_DELIVER 0x24
+#define GPIO_INT_BOTH_EDGES_DELIVER 0x28
+#define GPIO_INT_LEVEL_HIGH_DELIVER 0x22
+#define GPIO_INT_LEVEL_LOW_DELIVER 0x26
+#define GPIO_INT_EDGE_HIGH_STATUS_DELIVER 0x30
+#define GPIO_INT_EDGE_LOW_STATUS_DELIVER 0x34
+#define GPIO_INT_BOTH_EDGES_STATUS_DELIVER 0x38
+#define GPIO_INT_LEVEL_HIGH_STATUS_DELIVER 0x32
+#define GPIO_INT_LEVEL_LOW_STATUS_DELIVER 0x36
+#define GPIO_INT_FLAG 0x01
+#define GPIO_INT_INT_MASK 0x3e
+#define GPIO_INT_INT_NEG_SHIFT 1
+#define GPIO_INT_PULL_MASK 0xc0
+#define GPIO_INT_PULL_NEG_SHIFT 2
+
+/* Auxiliary definition for PAD_INT */
+#define PAD_CONTROL(interrupt, pull) \
+ (GPIO_INT ## _ ## interrupt | GPIO_INT ## _ ## pull)
+/* General purpose interrupt pad configuration */
+#define PAD_INT(pin, interrupt, pull) \
+ { .gpio = (pin), \
+ .function = pin ## _IOMUX_ ## GPIOxx, \
+ .control = PAD_CONTROL(interrupt, pull) | GPIO_INT_FLAG }
/* Native function pad configuration */
#define PAD_NF(pin, func, pull) \
{ .gpio = (pin), \
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index a2a54c2..1f7ca0f 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -175,8 +175,8 @@
void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr,
size_t size)
{
- void *tmp_ptr;
- uint8_t control, mux, index;
+ uint8_t *tmp_ptr;
+ uint8_t control, mux, index, interrupt, pull;
for (index = 0; index < size; index++) {
mux = gpio_ptr[index].function;
@@ -186,11 +186,21 @@
/*
* Get the address of AMD_GPIO_CONTROL (dword) relative
- * to the desired pin and program bits 16-23.
+ * to the desired pin and point to bits 16-23.
*/
- tmp_ptr = (void *)(gpio_ptr[index].gpio * sizeof(uint32_t) +
+ tmp_ptr = (uint8_t *)(gpio_ptr[index].gpio * sizeof(uint32_t) +
AMD_GPIO_CONTROL + 2);
- write8(tmp_ptr, control);
+ if ((control & GPIO_INT_FLAG) == GPIO_INT_FLAG) {
+ /* here if PAD_INT generated control */
+ interrupt = (control & GPIO_INT_INT_MASK) >>
+ GPIO_INT_INT_NEG_SHIFT;
+ pull = (control & GPIO_INT_PULL_MASK) >>
+ GPIO_INT_PULL_NEG_SHIFT;
+ write8(tmp_ptr, pull); /* pull goes to bits 16-23 */
+ tmp_ptr--; /* Point bits 8 - 15. */
+ write8(tmp_ptr, interrupt);
+ } else
+ write8(tmp_ptr, control);
}
}
--
To view, visit https://review.coreboot.org/25758
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22
Gerrit-Change-Number: 25758
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180420/ce2d0ea5/attachment-0001.html>
More information about the coreboot-gerrit
mailing list