<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25758">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">stoneyridge GPIO: Create and use PAD_INT for interrupt pins<br><br>The default interrupt control for GPIO pins within stoneyridge is for edge<br>triggered, high. However, sometimes these need to change, or maybe the<br>interrupt needs to be reported or delivered. This was the case of platform<br>grunt, where the interrupt related bits were being changed afterwards.<br>Ideally all the bits should be programmed through the same procedure.<br>Create a PAD_INT definition and change function sb_program_gpios() to accept<br>the output from PAD_INT and program all the necessary bits while keeping<br>compatibility with other PAD_XX definitions.<br><br>BUG=b:72875858<br>TEST=Add code to report GPIO configuration, build grunt and record a<br>baseline. Add new code, rebuild grunt and record a test output. Compare<br>baseline against test, there should be no change in GPIO programming.<br>Remove code that reports GPIO configuration.<br><br>Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/mainboard/google/kahlee/bootblock/bootblock.c<br>M src/mainboard/google/kahlee/variants/baseboard/gpio.c<br>M src/soc/amd/stoneyridge/include/soc/gpio.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>4 files changed, 80 insertions(+), 26 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/25758/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>index 1eb18f1..9c41d95 100644</span><br><span>--- a/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c</span><br><span>@@ -36,11 +36,4 @@</span><br><span> {</span><br><span> /* Setup TPM decode before verstage */</span><br><span> sb_tpm_decode_spi();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Configure cr50 interrupt pin for use in polling tpm status */</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) {</span><br><span style="color: hsl(0, 100%, 40%);">- const uint32_t flags = GPIO_EDGEL_TRIG | GPIO_ACTIVE_LOW |</span><br><span style="color: hsl(0, 100%, 40%);">- GPIO_INT_STATUS_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- gpio_set_interrupt(H1_PCH_INT, flags);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span> }</span><br><span>diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>index 209d5ea..5a93fe3 100644</span><br><span>--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c</span><br><span>@@ -30,16 +30,16 @@</span><br><span> PAD_GPO(GPIO_4, HIGH),</span><br><span> </span><br><span> /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_6, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_6, EDGE_HIGH, PULL_UP),</span><br><span> </span><br><span> /* GPIO_9 - H1_PCH_INT_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_9, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_9, EDGE_LOW_STATUS, PULL_UP),</span><br><span> </span><br><span> /* GPIO_15 - EC_IN_RW_OD */</span><br><span> PAD_GPI(GPIO_15, PULL_UP),</span><br><span> </span><br><span> /* GPIO_22 - EC_SCI_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_22, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_22, EDGE_HIGH, PULL_UP),</span><br><span> </span><br><span> /* GPIO_26 - APU_PCIE_RST_L */</span><br><span> PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),</span><br><span>@@ -80,16 +80,16 @@</span><br><span> PAD_GPO(GPIO_4, HIGH),</span><br><span> </span><br><span> /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_6, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_6, EDGE_HIGH, PULL_UP),</span><br><span> </span><br><span> /* GPIO_9 - H1_PCH_INT_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_9, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_9, EDGE_LOW_STATUS, PULL_UP),</span><br><span> </span><br><span> /* GPIO_15 - EC_IN_RW_OD */</span><br><span> PAD_GPI(GPIO_15, PULL_UP),</span><br><span> </span><br><span> /* GPIO_22 - EC_SCI_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_22, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_22, EDGE_HIGH, PULL_UP),</span><br><span> </span><br><span> /* GPIO_24 - EC_PCH_WAKE_L */</span><br><span> PAD_GPI(GPIO_24, PULL_UP),</span><br><span>@@ -142,7 +142,7 @@</span><br><span> PAD_GPI(GPIO_3, PULL_UP),</span><br><span> </span><br><span> /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_5, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_5, EDGE_HIGH, PULL_UP),</span><br><span> </span><br><span> /* GPIO_7 - APU_PWROK_OD (currently not used) */</span><br><span> PAD_GPI(GPIO_7, PULL_UP),</span><br><span>@@ -154,7 +154,7 @@</span><br><span> PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),</span><br><span> </span><br><span> /* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_11, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_11, EDGE_HIGH, PULL_UP),</span><br><span> </span><br><span> /* GPIO_12 - Unused (TP126) */</span><br><span> PAD_GPI(GPIO_12, PULL_UP),</span><br><span>@@ -163,7 +163,7 @@</span><br><span> PAD_GPI(GPIO_13, PULL_UP),</span><br><span> </span><br><span> /* GPIO_14 - APU_HP_INT_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_14, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_14, EDGE_HIGH, PULL_UP),</span><br><span> </span><br><span> /* GPIO_16 - USB_C0_OC_L */</span><br><span> PAD_NF(GPIO_16, USB_OC0_L, PULL_UP),</span><br><span>@@ -181,7 +181,7 @@</span><br><span> PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),</span><br><span> </span><br><span> /* GPIO_21 - APU_PEN_INT_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_21, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_21, EDGE_HIGH, PULL_UP),</span><br><span> </span><br><span> /* GPIO_24 - USB_A1_OC_ODL */</span><br><span> PAD_NF(GPIO_24, USB_OC3_L, PULL_UP),</span><br><span>@@ -309,7 +309,7 @@</span><br><span> PAD_GPI(GPIO_3, PULL_UP),</span><br><span> </span><br><span> /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_5, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_5, EDGE_HIGH, PULL_UP),</span><br><span> </span><br><span> /* GPIO_7 - APU_PWROK_OD (currently not used) */</span><br><span> PAD_GPI(GPIO_7, PULL_UP),</span><br><span>@@ -321,7 +321,7 @@</span><br><span> PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),</span><br><span> </span><br><span> /* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_11, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_11, EDGE_HIGH, PULL_UP),</span><br><span> </span><br><span> /* GPIO_12 - EN_PP3300_TRACKPAD */</span><br><span> PAD_GPO(GPIO_12, HIGH),</span><br><span>@@ -330,7 +330,7 @@</span><br><span> PAD_GPI(GPIO_13, PULL_UP),</span><br><span> </span><br><span> /* GPIO_14 - APU_HP_INT_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_14, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_14, EDGE_HIGH, PULL_UP),</span><br><span> </span><br><span> /* GPIO_16 - USB_C0_OC_L */</span><br><span> PAD_NF(GPIO_16, USB_OC0_L, PULL_UP),</span><br><span>@@ -348,7 +348,7 @@</span><br><span> PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),</span><br><span> </span><br><span> /* GPIO_21 - APU_PEN_INT_ODL, SCI */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_GPI(GPIO_21, PULL_UP),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_INT(GPIO_21, EDGE_HIGH, PULL_UP),</span><br><span> </span><br><span> /* GPIO_25 - SD_CD */</span><br><span> PAD_NF(GPIO_25, SD0_CD, PULL_UP),</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h</span><br><span>index 0f7ec1b..b408ab2 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/gpio.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h</span><br><span>@@ -335,6 +335,57 @@</span><br><span> #define GPIO_PULL_PULL_DOWN FCH_GPIO_PULL_DOWN_ENABLE</span><br><span> #define GPIO_PULL_PULL_NONE 0</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Definitions for PAD_INT. It uses the fact that the register bit 16</span><br><span style="color: hsl(120, 100%, 40%);">+ * (bit 0 of control) is the status of the pin(read-only) as a signal</span><br><span style="color: hsl(120, 100%, 40%);">+ * for the code to treat control differently. If bit 0 is set, control</span><br><span style="color: hsl(120, 100%, 40%);">+ * will be interpreted as:</span><br><span style="color: hsl(120, 100%, 40%);">+ * Bit 7 register bit 21 pull down</span><br><span style="color: hsl(120, 100%, 40%);">+ * Bit 6 register bit 20 pull up</span><br><span style="color: hsl(120, 100%, 40%);">+ * Bits 5-1 register bits 12-8 interrupt related bits.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_PULL_NONE 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_PULL_UP 0x40</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_PULL_DOWN 0x80</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_EDGE_HIGH 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_EDGE_LOW 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_BOTH_EDGES 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_LEVEL_HIGH 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_LEVEL_LOW 0x06</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_EDGE_HIGH 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_EDGE_LOW 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_BOTH_EDGES 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_LEVEL_HIGH 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_LEVEL_LOW 0x06</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_EDGE_HIGH_STATUS 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_EDGE_LOW_STATUS 0x14</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_BOTH_EDGES_STATUS 0x18</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_LEVEL_HIGH_STATUS 0x12</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_LEVEL_LOW_STATUS 0x16</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_EDGE_HIGH_DELIVER 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_EDGE_LOW_DELIVER 0x24</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_BOTH_EDGES_DELIVER 0x28</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_LEVEL_HIGH_DELIVER 0x22</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_LEVEL_LOW_DELIVER 0x26</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_EDGE_HIGH_STATUS_DELIVER 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_EDGE_LOW_STATUS_DELIVER 0x34</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_BOTH_EDGES_STATUS_DELIVER 0x38</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_LEVEL_HIGH_STATUS_DELIVER 0x32</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_LEVEL_LOW_STATUS_DELIVER 0x36</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_FLAG 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_INT_MASK 0x3e</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_INT_NEG_SHIFT 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_PULL_MASK 0xc0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_INT_PULL_NEG_SHIFT 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Auxiliary definition for PAD_INT */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PAD_CONTROL(interrupt, pull) \</span><br><span style="color: hsl(120, 100%, 40%);">+ (GPIO_INT ## _ ## interrupt | GPIO_INT ## _ ## pull)</span><br><span style="color: hsl(120, 100%, 40%);">+/* General purpose interrupt pad configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+#define PAD_INT(pin, interrupt, pull) \</span><br><span style="color: hsl(120, 100%, 40%);">+ { .gpio = (pin), \</span><br><span style="color: hsl(120, 100%, 40%);">+ .function = pin ## _IOMUX_ ## GPIOxx, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .control = PAD_CONTROL(interrupt, pull) | GPIO_INT_FLAG }</span><br><span> /* Native function pad configuration */</span><br><span> #define PAD_NF(pin, func, pull) \</span><br><span> { .gpio = (pin), \</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index a2a54c2..1f7ca0f 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -175,8 +175,8 @@</span><br><span> void sb_program_gpios(const struct soc_amd_stoneyridge_gpio *gpio_ptr,</span><br><span> size_t size)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- void *tmp_ptr;</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t control, mux, index;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *tmp_ptr;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t control, mux, index, interrupt, pull;</span><br><span> </span><br><span> for (index = 0; index < size; index++) {</span><br><span> mux = gpio_ptr[index].function;</span><br><span>@@ -186,11 +186,21 @@</span><br><span> </span><br><span> /*</span><br><span> * Get the address of AMD_GPIO_CONTROL (dword) relative</span><br><span style="color: hsl(0, 100%, 40%);">- * to the desired pin and program bits 16-23.</span><br><span style="color: hsl(120, 100%, 40%);">+ * to the desired pin and point to bits 16-23.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- tmp_ptr = (void *)(gpio_ptr[index].gpio * sizeof(uint32_t) +</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_ptr = (uint8_t *)(gpio_ptr[index].gpio * sizeof(uint32_t) +</span><br><span> AMD_GPIO_CONTROL + 2);</span><br><span style="color: hsl(0, 100%, 40%);">- write8(tmp_ptr, control);</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((control & GPIO_INT_FLAG) == GPIO_INT_FLAG) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* here if PAD_INT generated control */</span><br><span style="color: hsl(120, 100%, 40%);">+ interrupt = (control & GPIO_INT_INT_MASK) >></span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_INT_INT_NEG_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ pull = (control & GPIO_INT_PULL_MASK) >></span><br><span style="color: hsl(120, 100%, 40%);">+ GPIO_INT_PULL_NEG_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(tmp_ptr, pull); /* pull goes to bits 16-23 */</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp_ptr--; /* Point bits 8 - 15. */</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(tmp_ptr, interrupt);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(tmp_ptr, control);</span><br><span> }</span><br><span> }</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25758">change 25758</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22 </div>
<div style="display:none"> Gerrit-Change-Number: 25758 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>