[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Additional early LPC and SPI init

[Marc Jones (Code Review)]

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/25755


Change subject: soc/amd/stoneyridge: Additional early LPC and SPI init
......................................................................

soc/amd/stoneyridge: Additional early LPC and SPI init

Additional LPC and SPI setup needed to move AGESA out of the bootblock.
Setup the prefetch, sio decode, a bugfix for IR and a bugfix for SPI.

BUG=b:70558952
TEST=Boots with AGESA moved out of bootblock.

Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c
Signed-off-by: Marc Jones <marc.jones at scarletltd.com>
---
M src/soc/amd/stoneyridge/southbridge.c
1 file changed, 28 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/25755/1

diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 7465b64..c69047b 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -543,12 +543,40 @@
 	pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_END, 0xffff);
 }
 
+static void sb_lpc early_setup(void)
+{
+	uint32_t dword;
+
+	/* Enable SPI prefetch */
+	dword = pci_read_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL);
+	dword |= SPI_FROM_HOST_PREFETCH_EN | SPI_FROM_USB_PREFETCH_EN;
+	pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword);
+
+#if IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE)
+	/* Decode SIOs at 2E/2F and 4E/4F */
+	dword = pci_read_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
+	dword |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE;
+	pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, dword);
+#endif
+
+	/*
+	 * Set EC port active. Fix for IR if IMC is not enabled.
+	 * TODO: Needed? Move or remove?
+	 */
+	dword = pci_read_config32(SOC_LPC_DEV, EC_PORT_ADDRESS);
+	dword |= EC_PORT_ACTIVE;
+	pci_write_config32(SOC_LPC_DEV, EC_PORT_ADDRESS, dword);
+
+}
+
 void bootblock_fch_early_init(void)
 {
 	sb_enable_rom();
 	sb_lpc_port80();
 	sb_lpc_decode();
+	sb_lpc_early_setup();
 	sb_spibase();
+	sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
 	sb_acpi_mmio_decode();
 	enable_aoac_devices();
 }

-- 
To view, visit https://review.coreboot.org/25755
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c
Gerrit-Change-Number: 25755
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180420/987473d1/attachment.html>