<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25755">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Additional early LPC and SPI init<br><br>Additional LPC and SPI setup needed to move AGESA out of the bootblock.<br>Setup the prefetch, sio decode, a bugfix for IR and a bugfix for SPI.<br><br>BUG=b:70558952<br>TEST=Boots with AGESA moved out of bootblock.<br><br>Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c<br>Signed-off-by: Marc Jones <marc.jones@scarletltd.com><br>---<br>M src/soc/amd/stoneyridge/southbridge.c<br>1 file changed, 28 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/25755/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 7465b64..c69047b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -543,12 +543,40 @@</span><br><span>   pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_END, 0xffff);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void sb_lpc early_setup(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+    uint32_t dword;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+     /* Enable SPI prefetch */</span><br><span style="color: hsl(120, 100%, 40%);">+     dword = pci_read_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+  dword |= SPI_FROM_HOST_PREFETCH_EN | SPI_FROM_USB_PREFETCH_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+        pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_STONEYRIDGE_LEGACY_FREE)</span><br><span style="color: hsl(120, 100%, 40%);">+        /* Decode SIOs at 2E/2F and 4E/4F */</span><br><span style="color: hsl(120, 100%, 40%);">+  dword = pci_read_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+  dword |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE;</span><br><span style="color: hsl(120, 100%, 40%);">+     pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, dword);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+        /*</span><br><span style="color: hsl(120, 100%, 40%);">+     * Set EC port active. Fix for IR if IMC is not enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+       * TODO: Needed? Move or remove?</span><br><span style="color: hsl(120, 100%, 40%);">+       */</span><br><span style="color: hsl(120, 100%, 40%);">+   dword = pci_read_config32(SOC_LPC_DEV, EC_PORT_ADDRESS);</span><br><span style="color: hsl(120, 100%, 40%);">+      dword |= EC_PORT_ACTIVE;</span><br><span style="color: hsl(120, 100%, 40%);">+      pci_write_config32(SOC_LPC_DEV, EC_PORT_ADDRESS, dword);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void bootblock_fch_early_init(void)</span><br><span> {</span><br><span>  sb_enable_rom();</span><br><span>     sb_lpc_port80();</span><br><span>     sb_lpc_decode();</span><br><span style="color: hsl(120, 100%, 40%);">+      sb_lpc_early_setup();</span><br><span>        sb_spibase();</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */</span><br><span>     sb_acpi_mmio_decode();</span><br><span>       enable_aoac_devices();</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25755">change 25755</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25755"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c </div>
<div style="display:none"> Gerrit-Change-Number: 25755 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>