[coreboot-gerrit] Change in coreboot[master]: soc/cavium: Add PCI support
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Fri Apr 20 14:52:31 CEST 2018
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25750
Change subject: soc/cavium: Add PCI support
......................................................................
soc/cavium: Add PCI support
Tested on Cavium CN81XX_EVB.
All PCI devices are visible.
Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0
Signed-off-by: Patrick Rudolph <patrick.rudolph at 9elements.com>
---
M src/mainboard/cavium/cn8100_sff_evb/devicetree.cb
M src/soc/cavium/cn81xx/Makefile.inc
A src/soc/cavium/cn81xx/ecam0.c
A src/soc/cavium/cn81xx/include/soc/ecam0.h
M src/soc/cavium/cn81xx/soc.c
M src/soc/cavium/common/Kconfig
M src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c
7 files changed, 192 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/25750/1
diff --git a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb
index cd495e1..80d0a10 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb
+++ b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb
@@ -15,4 +15,71 @@
chip soc/cavium/cn81xx
device cpu_cluster 0 on end
+
+ device domain 0 on
+ device pci 01.0 on # PCI bridge
+ device pci 00.1 on end #RESET
+ device pci 00.2 on end #DAP
+ device pci 00.3 on end #MDIO
+ device pci 00.4 on end #FUSE
+
+ device pci 04.0 on end
+
+ device pci 06.0 on end #L2C
+ device pci 07.0 on end #L2C-CBC
+ device pci 07.4 on end #L2C-MCI
+
+ device pci 08.0 on end #UUA0
+ device pci 08.1 on end #UUA1
+ device pci 08.2 on end #UUA2
+ device pci 08.3 on end #UUA3
+ device pci 08.4 on end #VRM
+
+ device pci 09.0 on end #I2C0
+ device pci 09.1 on end #I2C1
+
+ device pci 0a.0 on end #PCC Bridge
+ device pci 0b.0 on end #IOBN
+ device pci 0c.0 on end #OCLA0
+ device pci 0c.1 on end #OCLA1
+
+ device pci 0d.0 on end
+
+ device pci 0e.0 on end # PCIe0
+ device pci 0e.1 on end # PCIe1
+ device pci 0e.2 on end # PCIe2
+
+ device pci 10.0 on end #bgx0
+ device pci 10.1 on end #bgx1
+
+ device pci 11.0 on end #rgx0
+
+ device pci 12.0 on end
+
+ device pci 1c.0 on end #GSER0
+ device pci 1c.1 on end #GSER1
+ device pci 1c.2 on end #GSER2
+ device pci 1c.3 on end #GSER3
+ end
+ device pci 02.0 on end #SMMU
+ device pci 03.0 on end #GIC
+ device pci 04.0 on end #GTI
+ device pci 05.0 off end
+
+ device pci 06.0 on end # GPIO
+ device pci 07.0 on end # SPI
+ device pci 08.0 on end # MIO
+ device pci 09.0 on end # PCI bridge
+ device pci 0a.0 on end # PCI bridge
+ device pci 0b.0 on end # NFC
+ device pci 0c.0 on end # PCI bridge
+ device pci 0d.0 on end
+ device pci 0e.0 on end # VRM
+ device pci 0f.0 on end # PCI bridge
+
+ device pci 10.0 on end
+ device pci 11.0 on end
+ device pci 16.0 on end
+ device pci 17.0 on end
+ end
end
diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc
index 8fd7daa..f98e890 100644
--- a/src/soc/cavium/cn81xx/Makefile.inc
+++ b/src/soc/cavium/cn81xx/Makefile.inc
@@ -64,6 +64,7 @@
ramstage-y += soc.c
ramstage-y += cpu.c
ramstage-y += l2c.c
+ramstage-y += ecam0.c
ramstage-y += bl31_plat_params.c
BL31_MAKEARGS += PLAT=t81 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" ENABLE_SPE_FOR_LOWER_ELS=0
diff --git a/src/soc/cavium/cn81xx/ecam0.c b/src/soc/cavium/cn81xx/ecam0.c
new file mode 100644
index 0000000..407f287
--- /dev/null
+++ b/src/soc/cavium/cn81xx/ecam0.c
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <soc/addressmap.h>
+
+/*
+ * Functions for accessing PCI configuration space with mmconf accesses
+ */
+#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE, MASK) \
+ ((void *)(((uintptr_t)ECAM_PF_BAR2 |\
+ (((SEGBUS) & 0xFFF) << 20) |\
+ (((DEVFN) & 0xFF) << 12) |\
+ ((WHERE) & 0xFFF)) & ~MASK))
+
+static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn,
+ int where)
+{
+ return read8(PCI_MMIO_ADDR(bus, devfn, where, 0));
+}
+
+static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn,
+ int where)
+{
+ return read16(PCI_MMIO_ADDR(bus, devfn, where, 1));
+}
+
+static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn,
+ int where)
+{
+ return read32(PCI_MMIO_ADDR(bus, devfn, where, 3));
+}
+
+static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn,
+ int where, uint8_t value)
+{
+ write8(PCI_MMIO_ADDR(bus, devfn, where, 0), value);
+}
+
+static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn,
+ int where, uint16_t value)
+{
+ write16(PCI_MMIO_ADDR(bus, devfn, where, 1), value);
+}
+
+static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn,
+ int where, uint32_t value)
+{
+ write32(PCI_MMIO_ADDR(bus, devfn, where, 3), value);
+}
+
+static const struct pci_bus_operations pci_ops_ecam0_mmconf = {
+ .read8 = pci_mmconf_read_config8,
+ .read16 = pci_mmconf_read_config16,
+ .read32 = pci_mmconf_read_config32,
+ .write8 = pci_mmconf_write_config8,
+ .write16 = pci_mmconf_write_config16,
+ .write32 = pci_mmconf_write_config32,
+};
+
+static const struct pci_bus_operations *pci_bus_ecam0_ops(device_t dev)
+{
+ return &pci_ops_ecam0_mmconf;
+}
+
+static void pci_domain_set_resources(device_t dev)
+{
+ assign_resources(dev->link_list);
+}
+
+struct device_operations pci_domain_ops_ecam0 = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_ecam0_ops,
+};
diff --git a/src/soc/cavium/cn81xx/include/soc/ecam0.h b/src/soc/cavium/cn81xx/include/soc/ecam0.h
new file mode 100644
index 0000000..8699410
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/ecam0.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ * Copyright 2018-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM0_H
+#define __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_ECAM0_H
+
+extern struct device_operations pci_domain_ops_ecam0;
+
+#endif
diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c
index ac4139e..3471ce2 100644
--- a/src/soc/cavium/cn81xx/soc.c
+++ b/src/soc/cavium/cn81xx/soc.c
@@ -28,6 +28,7 @@
#include <symbols.h>
#include <console/uart.h>
#include <fit.h>
+#include <soc/ecam0.h>
/* FIXME(dhendrix): Need TZRAM_* definitions from ATF for Cavium */
//#include <arm-trusted-firmware/plat/rockchip/ck3399/include/shared/bl31_param.h>
@@ -89,10 +90,13 @@
static void enable_soc_dev(device_t dev)
{
- dev->ops = &soc_ops;
+ if (dev->path.type == DEVICE_PATH_DOMAIN &&
+ dev->path.domain.domain == 0) {
+ dev->ops = &pci_domain_ops_ecam0;
+ }
}
struct chip_operations soc_cavium_cn81xx_ops = {
CHIP_NAME("SOC Cavium CN81XX")
- .enable_dev = enable_soc_dev,
+ .enable_dev = enable_soc_dev,
};
diff --git a/src/soc/cavium/common/Kconfig b/src/soc/cavium/common/Kconfig
index efa0288..1f68b99 100644
--- a/src/soc/cavium/common/Kconfig
+++ b/src/soc/cavium/common/Kconfig
@@ -4,7 +4,10 @@
select BOOTBLOCK_CUSTOM
select CAVIUM_BDK
select FLATTENED_DEVICE_TREE
+ select PCI
if SOC_CAVIUM_COMMON
+config MMCONF_SUPPORT
+ def_bool n
endif
diff --git a/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c b/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c
index e3e582d..7e0755c 100644
--- a/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c
+++ b/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c
@@ -94,7 +94,7 @@
bdk_fatal("PCIe CSR access not supported when PCIe not linked in\n");
#endif
/* FIXME(dhendrix) */
-#if !IS_ENABLED(CONFIG_PCI)
+#if !IS_ENABLED(CONFIG_PCI) || 1
bdk_fatal("PCIe CSR access not supported when PCIe not linked in\n");
#else
union bdk_pcc_dev_con_s dev_con;
@@ -215,7 +215,7 @@
bdk_fatal("PCIe CSR access not supported when PCIe not linked in\n");
#endif
/* FIXME(dhendrix) */
-#if !IS_ENABLED(CONFIG_PCI)
+#if !IS_ENABLED(CONFIG_PCI) || 1
bdk_fatal("PCIe CSR access not supported when PCIe not linked in\n");
#else
union bdk_pcc_dev_con_s dev_con;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0
Gerrit-Change-Number: 25750
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph at 9elements.com>
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