[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Set DISB after Dram init

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/25704


Change subject: soc/intel/cannonlake: Set DISB after Dram init
......................................................................

soc/intel/cannonlake: Set DISB after Dram init

DRAM Initialization Scratchpad Bit need to be set after Dram
Initialization finished.

BUG=None

Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/pmutil.c
M src/soc/intel/cannonlake/romstage/romstage.c
2 files changed, 14 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/25704/1

diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index a5d1833..3749b1c 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -128,6 +128,19 @@
 	return gpe_sts_bits;
 }
 
+void pmc_set_disb(void)
+{
+	/* Set the DISB after DRAM init */
+	uint8_t disb_val;
+
+	disb_val = read8(pmc_mmio_regs() + GEN_PMCON_A + 2);
+	disb_val |= DISB;
+
+	/* Don't clear bits that are write-1-to-clear */
+	disb_val &= ~(MS4V | SUS_PWR_FLR);
+	write8((pmc_mmio_regs() + GEN_PMCON_A + 2), disb_val);
+}
+
 /*
  * PMC controller gets hidden from PCI bus
  * during FSP-Silicon init call. Hence PWRMBASE
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index dc96526..c8cb927 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -123,6 +123,7 @@
 	timestamp_add_now(TS_START_ROMSTAGE);
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);
+	pmc_set_disb();
 	if (!s3wake)
 		save_dimm_info();
 	if (postcar_frame_init(&pcf, 1 * KiB))

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c
Gerrit-Change-Number: 25704
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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