<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25704">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Set DISB after Dram init<br><br>DRAM Initialization Scratchpad Bit need to be set after Dram<br>Initialization finished.<br><br>BUG=None<br><br>Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/pmutil.c<br>M src/soc/intel/cannonlake/romstage/romstage.c<br>2 files changed, 14 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/25704/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c</span><br><span>index a5d1833..3749b1c 100644</span><br><span>--- a/src/soc/intel/cannonlake/pmutil.c</span><br><span>+++ b/src/soc/intel/cannonlake/pmutil.c</span><br><span>@@ -128,6 +128,19 @@</span><br><span>      return gpe_sts_bits;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void pmc_set_disb(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+     /* Set the DISB after DRAM init */</span><br><span style="color: hsl(120, 100%, 40%);">+    uint8_t disb_val;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   disb_val = read8(pmc_mmio_regs() + GEN_PMCON_A + 2);</span><br><span style="color: hsl(120, 100%, 40%);">+  disb_val |= DISB;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+   /* Don't clear bits that are write-1-to-clear */</span><br><span style="color: hsl(120, 100%, 40%);">+  disb_val &= ~(MS4V | SUS_PWR_FLR);</span><br><span style="color: hsl(120, 100%, 40%);">+        write8((pmc_mmio_regs() + GEN_PMCON_A + 2), disb_val);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span>  * PMC controller gets hidden from PCI bus</span><br><span>  * during FSP-Silicon init call. Hence PWRMBASE</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>index dc96526..c8cb927 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>@@ -123,6 +123,7 @@</span><br><span>        timestamp_add_now(TS_START_ROMSTAGE);</span><br><span>        s3wake = pmc_fill_power_state(ps) == ACPI_S3;</span><br><span>        fsp_memory_init(s3wake);</span><br><span style="color: hsl(120, 100%, 40%);">+      pmc_set_disb();</span><br><span>      if (!s3wake)</span><br><span>                 save_dimm_info();</span><br><span>    if (postcar_frame_init(&pcf, 1 * KiB))</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25704">change 25704</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25704"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c </div>
<div style="display:none"> Gerrit-Change-Number: 25704 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>