[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: support more XMP timings

[Dan Elkouby (Code Review)]

Dan Elkouby has uploaded this change for review. ( https://review.coreboot.org/25664


Change subject: nb/intel/sandybridge: support more XMP timings
......................................................................

nb/intel/sandybridge: support more XMP timings

Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9
Signed-off-by: Dan Elkouby <streetwalkermc at gmail.com>
---
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_common.h
M src/northbridge/intel/sandybridge/raminit_ivy.c
M src/northbridge/intel/sandybridge/raminit_sandy.c
4 files changed, 14 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/25664/1

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 0a44220..d62927c 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -160,6 +160,8 @@
 		ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR);
 		ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP);
 		ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW);
+		ctrl->tCWL = MAX(ctrl->tCWL, dimm->tCWL);
+		ctrl->tCMD = MAX(ctrl->tCMD, dimm->tCMD);
 	}
 
 	if (!ctrl->cas_supported)
@@ -2356,6 +2358,8 @@
 		 * Try command rate 1T and 2T
 		 */
 		cmdrate = ((ctrl->rankmap[channel] & 0x5) == 0x5);
+		if (ctrl->tCMD)
+			cmdrate = MIN(DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK) - 1, 1);
 
 		for (; cmdrate < 2; cmdrate++) {
 			err = try_cmd_stretch(ctrl, channel, cmdrate << 1);
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index ab6e592..1f32dcd 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -94,6 +94,8 @@
 	u32 tWTR;
 	u32 tRTP;
 	u32 tFAW;
+	u32 tCWL;
+	u32 tCMD;
 	/* Latencies in terms of clock cycles
 	 * They are saved separately as they are needed for DRAM MRS commands*/
 	u8 CAS;			/* CAS read latency */
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c
index 675ac71..19dea2f 100644
--- a/src/northbridge/intel/sandybridge/raminit_ivy.c
+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c
@@ -479,7 +479,10 @@
 	/* DLL_CONFIG_MDLL_W_TIMER */
 	ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3;
 
-	ctrl->CWL = get_CWL(ctrl->tCK);
+	if (ctrl->tCWL)
+		ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK);
+	else
+		ctrl->CWL = get_CWL(ctrl->tCK);
 	printk(BIOS_DEBUG, "Selected CWL latency   : %uT\n", ctrl->CWL);
 
 	/* Find tRCD */
diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c
index 3acc563..99c107e 100644
--- a/src/northbridge/intel/sandybridge/raminit_sandy.c
+++ b/src/northbridge/intel/sandybridge/raminit_sandy.c
@@ -251,7 +251,10 @@
 	/* DLL_CONFIG_MDLL_W_TIMER */
 	ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3;
 
-	ctrl->CWL = get_CWL(ctrl->tCK);
+	if (ctrl->tCWL)
+		ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK);
+	else
+		ctrl->CWL = get_CWL(ctrl->tCK);
 	printk(BIOS_DEBUG, "Selected CWL latency   : %uT\n", ctrl->CWL);
 
 	/* Find tRCD */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9
Gerrit-Change-Number: 25664
Gerrit-PatchSet: 1
Gerrit-Owner: Dan Elkouby <streetwalkermc at gmail.com>
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