<p>Dan Elkouby has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25664">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/sandybridge: support more XMP timings<br><br>Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9<br>Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com><br>---<br>M src/northbridge/intel/sandybridge/raminit_common.c<br>M src/northbridge/intel/sandybridge/raminit_common.h<br>M src/northbridge/intel/sandybridge/raminit_ivy.c<br>M src/northbridge/intel/sandybridge/raminit_sandy.c<br>4 files changed, 14 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/25664/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>index 0a44220..d62927c 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>@@ -160,6 +160,8 @@</span><br><span> ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR);</span><br><span> ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP);</span><br><span> ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl->tCWL = MAX(ctrl->tCWL, dimm->tCWL);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl->tCMD = MAX(ctrl->tCMD, dimm->tCMD);</span><br><span> }</span><br><span> </span><br><span> if (!ctrl->cas_supported)</span><br><span>@@ -2356,6 +2358,8 @@</span><br><span> * Try command rate 1T and 2T</span><br><span> */</span><br><span> cmdrate = ((ctrl->rankmap[channel] & 0x5) == 0x5);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ctrl->tCMD)</span><br><span style="color: hsl(120, 100%, 40%);">+ cmdrate = MIN(DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK) - 1, 1);</span><br><span> </span><br><span> for (; cmdrate < 2; cmdrate++) {</span><br><span> err = try_cmd_stretch(ctrl, channel, cmdrate << 1);</span><br><span>diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h</span><br><span>index ab6e592..1f32dcd 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit_common.h</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit_common.h</span><br><span>@@ -94,6 +94,8 @@</span><br><span> u32 tWTR;</span><br><span> u32 tRTP;</span><br><span> u32 tFAW;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tCWL;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tCMD;</span><br><span> /* Latencies in terms of clock cycles</span><br><span> * They are saved separately as they are needed for DRAM MRS commands*/</span><br><span> u8 CAS; /* CAS read latency */</span><br><span>diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c</span><br><span>index 675ac71..19dea2f 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit_ivy.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c</span><br><span>@@ -479,7 +479,10 @@</span><br><span> /* DLL_CONFIG_MDLL_W_TIMER */</span><br><span> ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- ctrl->CWL = get_CWL(ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ctrl->tCWL)</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl->CWL = get_CWL(ctrl->tCK);</span><br><span> printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL);</span><br><span> </span><br><span> /* Find tRCD */</span><br><span>diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c</span><br><span>index 3acc563..99c107e 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit_sandy.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit_sandy.c</span><br><span>@@ -251,7 +251,10 @@</span><br><span> /* DLL_CONFIG_MDLL_W_TIMER */</span><br><span> ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- ctrl->CWL = get_CWL(ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ctrl->tCWL)</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrl->CWL = get_CWL(ctrl->tCK);</span><br><span> printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL);</span><br><span> </span><br><span> /* Find tRCD */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25664">change 25664</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9 </div>
<div style="display:none"> Gerrit-Change-Number: 25664 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Dan Elkouby <streetwalkermc@gmail.com> </div>