[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Configure PCIe root port #1 for APL WiFi
Venkateswarlu V Vinjamuri (Code Review)
gerrit at coreboot.org
Thu Apr 12 19:27:22 CEST 2018
Venkateswarlu V Vinjamuri has uploaded this change for review. ( https://review.coreboot.org/25637
Change subject: soc/intel/apollolake: Configure PCIe root port #1 for APL WiFi
......................................................................
soc/intel/apollolake: Configure PCIe root port #1 for APL WiFi
APL uses PCIe root port 1 (PCIe ID 14.0) for discrete PCIe wifi card.
BUG=None
BRANCH=None
TEST=Use Stone Peak discrete wifi card and test s0ix.
Change-Id: Ia81722f4533916fe93009a73d86765e5de9dab08
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
---
M src/soc/intel/apollolake/acpi/pcie.asl
M src/soc/intel/apollolake/chip.c
2 files changed, 4 insertions(+), 106 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/25637/1
diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl
index 050f2f0..da99591 100644
--- a/src/soc/intel/apollolake/acpi/pcie.asl
+++ b/src/soc/intel/apollolake/acpi/pcie.asl
@@ -13,114 +13,12 @@
* GNU General Public License for more details.
*/
+/* PCIe Ports */
+
Device (RP01)
{
Name (_ADR, 0x00140000)
Name (_DDN, "PCIe-B 0")
- Name (PDST, 0) /* present Detect status */
- /* lowest D-state supported by
- * PCIe root port during S0 state
- */
- Name (_S0W, 4)
-
- /* Dynamic Opregion needed to access registers
- * when the controller is in D3 cold
- */
- OperationRegion (PX01, PCI_Config, 0x00, 0xFF)
- Field (PX01, AnyAcc, NoLock, Preserve)
- {
- Offset(0x5A),
- , 6,
- PDS, 1, /* 6, Presence detect Change */
- Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */
- , 2,
- L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
- L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
- Offset(0xF4), /* BLKPLLEN */
- , 10,
- BPLL, 1,
- }
-
- OperationRegion (PX02, PCI_Config, 0x338, 0x4)
- Field (PX02, AnyAcc, NoLock, Preserve)
- {
- , 26,
- BDQA, 1 /* BLKDQDA */
- }
-
- PowerResource (PXP, 0, 0)
- {
- /* Define the PowerResource for PCIe slot */
- Method (_STA, 0, Serialized)
- {
- Store (PDS, PDST)
- If (LEqual (PDS, 1)) {
- Return (0xf)
- } Else {
- Return (0)
- }
- }
-
- Method (_ON, 0, Serialized)
- {
- If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
- /* Enter this condition if device
- * is connected
- */
-
- /* De-assert PERST */
- \_SB.PCI0.PRDA (\PRT0)
-
- Store (0, BDQA) /* Set BLKDQDA to 0 */
- Store (0, BPLL) /* Set BLKPLLEN to 0 */
-
- /* Set L23_Rdy to Detect Transition
- * (L23R2DT)
- */
- Store (1, L23R)
- Sleep (16)
- Store (0, Local0)
-
- /* Delay for transition Detect
- * and link to train
- */
- While (L23R) {
- If (Lgreater (Local0, 4)) {
- Break
- }
- Sleep (16)
- Increment (Local0)
- }
- } /* End PDS condition check */
- }
-
- Method (_OFF, 0, Serialized)
- {
- /* Set L23_Rdy Entry Request (L23ER) */
- If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
- /* enter this condition if device
- * is connected
- */
- Store (1, L23E)
- Sleep (16)
- Store (0, Local0)
- While (L23E) {
- If (Lgreater (Local0, 4)) {
- Break
- }
- Sleep (16)
- Increment (Local0)
- }
- Store (1, BDQA) /* Set BLKDQDA to 1 */
- Store (1, BPLL) /* Set BLKPLLEN to 1 */
-
- /* Assert PERST */
- \_SB.PCI0.PRAS (\PRT0)
- } /* End PDS condition check */
- } /* End of Method_OFF */
- } /* End PXP */
-
- Name(_PR0, Package() { PXP })
- Name(_PR3, Package() { PXP })
+ #include "pcie_port.asl"
}
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 1dd6daf..324fb9f 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -111,7 +111,7 @@
case PCH_DEVFN_SDIO:
return "SDIO";
/* PCIe */
- case PCH_DEVFN_PCIE1:
+ case PCH_DEVFN_PCIE5:
return "RP01";
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia81722f4533916fe93009a73d86765e5de9dab08
Gerrit-Change-Number: 25637
Gerrit-PatchSet: 1
Gerrit-Owner: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
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