<p>Venkateswarlu V Vinjamuri has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25637">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Configure PCIe root port #1 for APL WiFi<br><br>APL uses PCIe root port 1 (PCIe ID 14.0) for discrete PCIe wifi card.<br><br>BUG=None<br>BRANCH=None<br>TEST=Use Stone Peak discrete wifi card and test s0ix.<br><br>Change-Id: Ia81722f4533916fe93009a73d86765e5de9dab08<br>Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com><br>---<br>M src/soc/intel/apollolake/acpi/pcie.asl<br>M src/soc/intel/apollolake/chip.c<br>2 files changed, 4 insertions(+), 106 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/25637/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl</span><br><span>index 050f2f0..da99591 100644</span><br><span>--- a/src/soc/intel/apollolake/acpi/pcie.asl</span><br><span>+++ b/src/soc/intel/apollolake/acpi/pcie.asl</span><br><span>@@ -13,114 +13,12 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* PCIe Ports */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> Device (RP01)</span><br><span> {</span><br><span> Name (_ADR, 0x00140000)</span><br><span> Name (_DDN, "PCIe-B 0")</span><br><span style="color: hsl(0, 100%, 40%);">- Name (PDST, 0) /* present Detect status */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* lowest D-state supported by</span><br><span style="color: hsl(0, 100%, 40%);">- * PCIe root port during S0 state</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- Name (_S0W, 4)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Dynamic Opregion needed to access registers</span><br><span style="color: hsl(0, 100%, 40%);">- * when the controller is in D3 cold</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- OperationRegion (PX01, PCI_Config, 0x00, 0xFF)</span><br><span style="color: hsl(0, 100%, 40%);">- Field (PX01, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0x5A),</span><br><span style="color: hsl(0, 100%, 40%);">- , 6,</span><br><span style="color: hsl(0, 100%, 40%);">- PDS, 1, /* 6, Presence detect Change */</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */</span><br><span style="color: hsl(0, 100%, 40%);">- , 2,</span><br><span style="color: hsl(0, 100%, 40%);">- L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */</span><br><span style="color: hsl(0, 100%, 40%);">- L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */</span><br><span style="color: hsl(0, 100%, 40%);">- Offset(0xF4), /* BLKPLLEN */</span><br><span style="color: hsl(0, 100%, 40%);">- , 10,</span><br><span style="color: hsl(0, 100%, 40%);">- BPLL, 1,</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- OperationRegion (PX02, PCI_Config, 0x338, 0x4)</span><br><span style="color: hsl(0, 100%, 40%);">- Field (PX02, AnyAcc, NoLock, Preserve)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- , 26,</span><br><span style="color: hsl(0, 100%, 40%);">- BDQA, 1 /* BLKDQDA */</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- PowerResource (PXP, 0, 0)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Define the PowerResource for PCIe slot */</span><br><span style="color: hsl(0, 100%, 40%);">- Method (_STA, 0, Serialized)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- Store (PDS, PDST)</span><br><span style="color: hsl(0, 100%, 40%);">- If (LEqual (PDS, 1)) {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (0xf)</span><br><span style="color: hsl(0, 100%, 40%);">- } Else {</span><br><span style="color: hsl(0, 100%, 40%);">- Return (0)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Method (_ON, 0, Serialized)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enter this condition if device</span><br><span style="color: hsl(0, 100%, 40%);">- * is connected</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* De-assert PERST */</span><br><span style="color: hsl(0, 100%, 40%);">- \_SB.PCI0.PRDA (\PRT0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Store (0, BDQA) /* Set BLKDQDA to 0 */</span><br><span style="color: hsl(0, 100%, 40%);">- Store (0, BPLL) /* Set BLKPLLEN to 0 */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set L23_Rdy to Detect Transition</span><br><span style="color: hsl(0, 100%, 40%);">- * (L23R2DT)</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- Store (1, L23R)</span><br><span style="color: hsl(0, 100%, 40%);">- Sleep (16)</span><br><span style="color: hsl(0, 100%, 40%);">- Store (0, Local0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Delay for transition Detect</span><br><span style="color: hsl(0, 100%, 40%);">- * and link to train</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- While (L23R) {</span><br><span style="color: hsl(0, 100%, 40%);">- If (Lgreater (Local0, 4)) {</span><br><span style="color: hsl(0, 100%, 40%);">- Break</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- Sleep (16)</span><br><span style="color: hsl(0, 100%, 40%);">- Increment (Local0)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- } /* End PDS condition check */</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Method (_OFF, 0, Serialized)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set L23_Rdy Entry Request (L23ER) */</span><br><span style="color: hsl(0, 100%, 40%);">- If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* enter this condition if device</span><br><span style="color: hsl(0, 100%, 40%);">- * is connected</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- Store (1, L23E)</span><br><span style="color: hsl(0, 100%, 40%);">- Sleep (16)</span><br><span style="color: hsl(0, 100%, 40%);">- Store (0, Local0)</span><br><span style="color: hsl(0, 100%, 40%);">- While (L23E) {</span><br><span style="color: hsl(0, 100%, 40%);">- If (Lgreater (Local0, 4)) {</span><br><span style="color: hsl(0, 100%, 40%);">- Break</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- Sleep (16)</span><br><span style="color: hsl(0, 100%, 40%);">- Increment (Local0)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- Store (1, BDQA) /* Set BLKDQDA to 1 */</span><br><span style="color: hsl(0, 100%, 40%);">- Store (1, BPLL) /* Set BLKPLLEN to 1 */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Assert PERST */</span><br><span style="color: hsl(0, 100%, 40%);">- \_SB.PCI0.PRAS (\PRT0)</span><br><span style="color: hsl(0, 100%, 40%);">- } /* End PDS condition check */</span><br><span style="color: hsl(0, 100%, 40%);">- } /* End of Method_OFF */</span><br><span style="color: hsl(0, 100%, 40%);">- } /* End PXP */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Name(_PR0, Package() { PXP })</span><br><span style="color: hsl(0, 100%, 40%);">- Name(_PR3, Package() { PXP })</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "pcie_port.asl"</span><br><span> }</span><br><span>diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c</span><br><span>index 1dd6daf..324fb9f 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.c</span><br><span>+++ b/src/soc/intel/apollolake/chip.c</span><br><span>@@ -111,7 +111,7 @@</span><br><span> case PCH_DEVFN_SDIO:</span><br><span> return "SDIO";</span><br><span> /* PCIe */</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_PCIE1:</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCH_DEVFN_PCIE5:</span><br><span> return "RP01";</span><br><span> }</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25637">change 25637</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia81722f4533916fe93009a73d86765e5de9dab08 </div>
<div style="display:none"> Gerrit-Change-Number: 25637 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> </div>