[coreboot-gerrit] Change in coreboot[master]: nb/intel/pineview: Enable and allocate 8M for TSEG

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25593


Change subject: nb/intel/pineview: Enable and allocate 8M for TSEG
......................................................................

nb/intel/pineview: Enable and allocate 8M for TSEG

TSEG can be used as a stage cache and SMM can be relocated here.

Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/pineview/pineview.h
M src/northbridge/intel/pineview/raminit.c
2 files changed, 7 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/25593/1

diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
index a2cda84..9873d4d 100644
--- a/src/northbridge/intel/pineview/pineview.h
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -62,7 +62,7 @@
 #define REMAPBASE	0x98
 #define REMAPLIMIT	0x9a
 #define SMRAM		0x9d	/* System Management RAM Control */
-#define ESMRAM		0x9e	/* Extended System Management RAM Control */
+#define ESMRAMC		0x9e	/* Extended System Management RAM Control */
 
 #define TOM		0xa0
 #define TOUUD		0xa2
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 1f03820..98addb1 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -2040,7 +2040,7 @@
 	gttsize = ggc_to_gtt[(ggc & 0x300) >> 8];
 	tom = s->channel_capacity[0];
 
-	tsegsize = 0x1; // 1MB
+	tsegsize = 0x8; // 1MB
 	mmiosize = 0x400; // 1GB
 
 	reclaim = false;
@@ -2075,6 +2075,11 @@
 	pci_write_config32(PCI_DEV(0,0,0), BGSM, gttbase << 20);
 	pci_write_config32(PCI_DEV(0,0,0), TSEG, tsegbase << 20);
 
+	u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
+	reg8 &= ~0x7;
+	reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
+	pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8);
+
 	printk(BIOS_DEBUG, "GBSM (igd) = verified %08x (written %08x)\n",
 		pci_read_config32(PCI_DEV(0,0,0), GBSM), gfxbase << 20);
 	printk(BIOS_DEBUG, "BGSM (gtt) = verified %08x (written %08x)\n",

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161
Gerrit-Change-Number: 25593
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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