[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add option for LPC decode

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/25574


Change subject: soc/intel/common: Add option for LPC decode
......................................................................

soc/intel/common: Add option for LPC decode

For SOC like skylake and cannonlake, LPC generic IO decoder need to
programmed to both LPC/ESPI PCI registers and DMI PCR registers. Which
had been done in early bootblock stage, no need to reprogram that again.

BUG=None
TEST=Enable COMMON_BLOCK_LPC_DMI_DECODE in config file, build and boot
up meowth board, there's no error message about "LPC: Cannot Open IO
Window:".

Change-Id: Iac49e19af233f1105b6120a95fd9cd0bcb44e7d7
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/common/block/lpc/Kconfig
M src/soc/intel/common/block/lpc/lpc_lib.c
2 files changed, 15 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/25574/1

diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig
index 41e72c4..9537611 100644
--- a/src/soc/intel/common/block/lpc/Kconfig
+++ b/src/soc/intel/common/block/lpc/Kconfig
@@ -11,3 +11,12 @@
 	help
 	  By default COMA range to LPC is enable. COMB range to LPC is optional
 	  and should select based on platform dedicated selection.
+
+config SOC_INTEL_COMMON_BLOCK_LPC_DMI_DECODE
+	depends on SOC_INTEL_COMMON_BLOCK_LPC
+	bool
+	default n
+	help
+	  Generic range IO Cycles received from DMI interface will need LPC
+	  decoding.
+
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index aeac441..594b1b8 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -69,6 +69,12 @@
 	uint32_t lgir_reg_offset, lgir, window_size, alignment;
 	resource_t bridged_size, bridge_base;
 
+	/* For platform that have PCH connect to CPU with OPDMI bus, LPC
+	 * generic IO decoding have been programmed in bootblock stage.
+	 * */
+	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_DMI_DECODE))
+		return;
+
 	printk(BIOS_SPEW, "LPC: Trying to open IO window from %x size %x\n",
 				base, size);
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iac49e19af233f1105b6120a95fd9cd0bcb44e7d7
Gerrit-Change-Number: 25574
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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