<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25574">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common: Add option for LPC decode<br><br>For SOC like skylake and cannonlake, LPC generic IO decoder need to<br>programmed to both LPC/ESPI PCI registers and DMI PCR registers. Which<br>had been done in early bootblock stage, no need to reprogram that again.<br><br>BUG=None<br>TEST=Enable COMMON_BLOCK_LPC_DMI_DECODE in config file, build and boot<br>up meowth board, there's no error message about "LPC: Cannot Open IO<br>Window:".<br><br>Change-Id: Iac49e19af233f1105b6120a95fd9cd0bcb44e7d7<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/common/block/lpc/Kconfig<br>M src/soc/intel/common/block/lpc/lpc_lib.c<br>2 files changed, 15 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/25574/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig</span><br><span>index 41e72c4..9537611 100644</span><br><span>--- a/src/soc/intel/common/block/lpc/Kconfig</span><br><span>+++ b/src/soc/intel/common/block/lpc/Kconfig</span><br><span>@@ -11,3 +11,12 @@</span><br><span> help</span><br><span> By default COMA range to LPC is enable. COMB range to LPC is optional</span><br><span> and should select based on platform dedicated selection.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BLOCK_LPC_DMI_DECODE</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on SOC_INTEL_COMMON_BLOCK_LPC</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Generic range IO Cycles received from DMI interface will need LPC</span><br><span style="color: hsl(120, 100%, 40%);">+ decoding.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>index aeac441..594b1b8 100644</span><br><span>--- a/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>+++ b/src/soc/intel/common/block/lpc/lpc_lib.c</span><br><span>@@ -69,6 +69,12 @@</span><br><span> uint32_t lgir_reg_offset, lgir, window_size, alignment;</span><br><span> resource_t bridged_size, bridge_base;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* For platform that have PCH connect to CPU with OPDMI bus, LPC</span><br><span style="color: hsl(120, 100%, 40%);">+ * generic IO decoding have been programmed in bootblock stage.</span><br><span style="color: hsl(120, 100%, 40%);">+ * */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_DMI_DECODE))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> printk(BIOS_SPEW, "LPC: Trying to open IO window from %x size %x\n",</span><br><span> base, size);</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25574">change 25574</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25574"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iac49e19af233f1105b6120a95fd9cd0bcb44e7d7 </div>
<div style="display:none"> Gerrit-Change-Number: 25574 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>