[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/gspi: Set Clock Update Bit for clock updates.

[Shamile Khan (Code Review)]

Shamile Khan has uploaded this change for review. ( https://review.coreboot.org/25573


Change subject: soc/intel/common/block/gspi: Set Clock Update Bit for clock updates.
......................................................................

soc/intel/common/block/gspi: Set Clock Update Bit for clock updates.

This is required for clock parameter settings to take effect.

BUG=b:75306520
BRANCH=None
TEST=On Octopus, used a scope to check that spi_clk fed to tpm is
1 MHz

Change-Id: Icdb617aa4aa944d46b3a56dab88d2008b01dea0d
Signed-off-by: Shamile Khan <shamile.khan at intel.com>
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 2 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/25573/1

diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index 60c7391..d86fd27 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -464,7 +464,8 @@
 	 * Program m/n divider.
 	 * Set m and n to 1, so that this divider acts as a pass-through.
 	 */
-	clocks = (1 << CLOCKS_N_SHIFT) | (1 << CLOCKS_M_SHIFT) | CLOCKS_ENABLE;
+	clocks = (1 << CLOCKS_N_SHIFT) | (1 << CLOCKS_M_SHIFT) | CLOCKS_ENABLE |
+		 CLOCKS_UPDATE;
 	gspi_write_mmio_reg(p, CLOCKS, clocks);
 	udelay(10);
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icdb617aa4aa944d46b3a56dab88d2008b01dea0d
Gerrit-Change-Number: 25573
Gerrit-PatchSet: 1
Gerrit-Owner: Shamile Khan <shamile.khan at intel.com>
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