[coreboot-gerrit] Change in coreboot[master]: Correct "MTTR" to "MTRR"
Jonathan Neuschäfer (Code Review)
gerrit at coreboot.org
Mon Apr 9 20:16:27 CEST 2018
Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/25568
Change subject: Correct "MTTR" to "MTRR"
......................................................................
Correct "MTTR" to "MTRR"
The term MTRR has been misspelled in a few places.
Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/cpu/x86/mtrr/mtrr.c
M src/drivers/intel/fsp1_1/stack.c
M src/soc/intel/broadwell/romstage/stack.c
M src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
M src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h
8 files changed, 17 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/25568/1
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 6678441..2788448 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -441,7 +441,7 @@
if (var_state->mtrr_index >= bios_mtrrs)
printk(BIOS_WARNING, "Taking a reserved OS MTRR.\n");
if (var_state->mtrr_index >= total_mtrrs) {
- printk(BIOS_ERR, "ERROR: Not enough MTRRs available! MTRR index is %d with %d MTTRs in total.\n",
+ printk(BIOS_ERR, "ERROR: Not enough MTRRs available! MTRR index is %d with %d MTRRs in total.\n",
var_state->mtrr_index, total_mtrrs);
return;
}
diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
index 639cf38..e4b30dd 100644
--- a/src/drivers/intel/fsp1_1/stack.c
+++ b/src/drivers/intel/fsp1_1/stack.c
@@ -36,7 +36,7 @@
uint32_t num_mtrrs;
uint32_t *slot;
- /* Display the MTTRs */
+ /* Display the MTRRs */
soc_display_mtrrs();
/* Top of stack needs to be aligned to a 8-byte boundary. */
diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c
index f17cd82..a6a4b4b 100644
--- a/src/soc/intel/broadwell/romstage/stack.c
+++ b/src/soc/intel/broadwell/romstage/stack.c
@@ -47,18 +47,18 @@
* of physical address bits. */
mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
- /* The order for each MTTR is value then base with upper 32-bits of
+ /* The order for each MTRR is value then base with upper 32-bits of
* each value coming before the lower 32-bits. The reasoning for
* this ordering is to create a stack layout like the following:
* +0: Number of MTRRs
- * +4: MTTR base 0 31:0
- * +8: MTTR base 0 63:32
- * +12: MTTR mask 0 31:0
- * +16: MTTR mask 0 63:32
- * +20: MTTR base 1 31:0
- * +24: MTTR base 1 63:32
- * +28: MTTR mask 1 31:0
- * +32: MTTR mask 1 63:32
+ * +4: MTRR base 0 31:0
+ * +8: MTRR base 0 63:32
+ * +12: MTRR mask 0 31:0
+ * +16: MTRR mask 0 63:32
+ * +20: MTRR base 1 31:0
+ * +24: MTRR base 1 63:32
+ * +28: MTRR mask 1 31:0
+ * +32: MTRR mask 1 63:32
*/
/* Cache the ROM as WP just below 4GiB. */
@@ -97,7 +97,7 @@
slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
num_mtrrs++;
- /* Save the number of MTTRs to setup. Return the stack location
+ /* Save the number of MTRRs to setup. Return the stack location
* pointing to the number of MTRRs. */
slot = stack_push(slot, num_mtrrs);
diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
index fc7d0e4..f444852 100644
--- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
@@ -1348,7 +1348,7 @@
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
- # setup MTTRs for stacks
+ # setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
index 45ed294..0fbcf77 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
@@ -1084,7 +1084,7 @@
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
- # setup MTTRs for stacks
+ # setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
index c744e47..2399bec 100644
--- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
@@ -1063,7 +1063,7 @@
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
- # setup MTTRs for stacks
+ # setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
index 5a4f7b9..7e12db1 100644
--- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
@@ -1063,7 +1063,7 @@
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
- # setup MTTRs for stacks
+ # setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h b/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h
index ef9970d..fb3e6ba 100644
--- a/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h
+++ b/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h
@@ -47,7 +47,7 @@
@retval EFI_SUCCESS Mtrr are set successfully.
@retval EFI_LOAD_ERROR No empty MTRRs to use.
@retval EFI_INVALID_PARAMETER The input parameter is not valid.
- @retval others An error occurs when setting MTTR.
+ @retval others An error occurs when setting MTRR.
**/
EFI_STATUS
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74
Gerrit-Change-Number: 25568
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
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