<p>Jonathan Neuschäfer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25568">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Correct "MTTR" to "MTRR"<br><br>The term MTRR has been misspelled in a few places.<br><br>Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74<br>Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net><br>---<br>M src/cpu/x86/mtrr/mtrr.c<br>M src/drivers/intel/fsp1_1/stack.c<br>M src/soc/intel/broadwell/romstage/stack.c<br>M src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc<br>M src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc<br>M src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc<br>M src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc<br>M src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h<br>8 files changed, 17 insertions(+), 17 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/25568/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c</span><br><span>index 6678441..2788448 100644</span><br><span>--- a/src/cpu/x86/mtrr/mtrr.c</span><br><span>+++ b/src/cpu/x86/mtrr/mtrr.c</span><br><span>@@ -441,7 +441,7 @@</span><br><span> if (var_state->mtrr_index >= bios_mtrrs)</span><br><span> printk(BIOS_WARNING, "Taking a reserved OS MTRR.\n");</span><br><span> if (var_state->mtrr_index >= total_mtrrs) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "ERROR: Not enough MTRRs available! MTRR index is %d with %d MTTRs in total.\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "ERROR: Not enough MTRRs available! MTRR index is %d with %d MTRRs in total.\n",</span><br><span> var_state->mtrr_index, total_mtrrs);</span><br><span> return;</span><br><span> }</span><br><span>diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c</span><br><span>index 639cf38..e4b30dd 100644</span><br><span>--- a/src/drivers/intel/fsp1_1/stack.c</span><br><span>+++ b/src/drivers/intel/fsp1_1/stack.c</span><br><span>@@ -36,7 +36,7 @@</span><br><span> uint32_t num_mtrrs;</span><br><span> uint32_t *slot;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Display the MTTRs */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Display the MTRRs */</span><br><span> soc_display_mtrrs();</span><br><span> </span><br><span> /* Top of stack needs to be aligned to a 8-byte boundary. */</span><br><span>diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c</span><br><span>index f17cd82..a6a4b4b 100644</span><br><span>--- a/src/soc/intel/broadwell/romstage/stack.c</span><br><span>+++ b/src/soc/intel/broadwell/romstage/stack.c</span><br><span>@@ -47,18 +47,18 @@</span><br><span> * of physical address bits. */</span><br><span> mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* The order for each MTTR is value then base with upper 32-bits of</span><br><span style="color: hsl(120, 100%, 40%);">+ /* The order for each MTRR is value then base with upper 32-bits of</span><br><span> * each value coming before the lower 32-bits. The reasoning for</span><br><span> * this ordering is to create a stack layout like the following:</span><br><span> * +0: Number of MTRRs</span><br><span style="color: hsl(0, 100%, 40%);">- * +4: MTTR base 0 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +8: MTTR base 0 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- * +12: MTTR mask 0 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +16: MTTR mask 0 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- * +20: MTTR base 1 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +24: MTTR base 1 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- * +28: MTTR mask 1 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +32: MTTR mask 1 63:32</span><br><span style="color: hsl(120, 100%, 40%);">+ * +4: MTRR base 0 31:0</span><br><span style="color: hsl(120, 100%, 40%);">+ * +8: MTRR base 0 63:32</span><br><span style="color: hsl(120, 100%, 40%);">+ * +12: MTRR mask 0 31:0</span><br><span style="color: hsl(120, 100%, 40%);">+ * +16: MTRR mask 0 63:32</span><br><span style="color: hsl(120, 100%, 40%);">+ * +20: MTRR base 1 31:0</span><br><span style="color: hsl(120, 100%, 40%);">+ * +24: MTRR base 1 63:32</span><br><span style="color: hsl(120, 100%, 40%);">+ * +28: MTRR mask 1 31:0</span><br><span style="color: hsl(120, 100%, 40%);">+ * +32: MTRR mask 1 63:32</span><br><span> */</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span>@@ -97,7 +97,7 @@</span><br><span> slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);</span><br><span> num_mtrrs++;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the number of MTTRs to setup. Return the stack location</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Save the number of MTRRs to setup. Return the stack location</span><br><span> * pointing to the number of MTRRs. */</span><br><span> slot = stack_push(slot, num_mtrrs);</span><br><span> </span><br><span>diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc</span><br><span>index fc7d0e4..f444852 100644</span><br><span>--- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc</span><br><span>+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc</span><br><span>@@ -1348,7 +1348,7 @@</span><br><span> mov $TOP_MEM2, %ecx # MSR:C001_001D</span><br><span> _WRMSR</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # setup MTTRs for stacks</span><br><span style="color: hsl(120, 100%, 40%);">+ # setup MTRRs for stacks</span><br><span> # A speculative read can be generated by a speculative fetch mis-aligned in a code zone</span><br><span> # or due to a data zone being interpreted as code. When a speculative read occurs outside a</span><br><span> # controlled region (intentionally used by software), it could cause an unwanted cache eviction.</span><br><span>diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc</span><br><span>index 45ed294..0fbcf77 100644</span><br><span>--- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc</span><br><span>+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc</span><br><span>@@ -1084,7 +1084,7 @@</span><br><span> mov $TOP_MEM2, %ecx # MSR:C001_001D</span><br><span> _WRMSR</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # setup MTTRs for stacks</span><br><span style="color: hsl(120, 100%, 40%);">+ # setup MTRRs for stacks</span><br><span> # A speculative read can be generated by a speculative fetch mis-aligned in a code zone</span><br><span> # or due to a data zone being interpreted as code. When a speculative read occurs outside a</span><br><span> # controlled region (intentionally used by software), it could cause an unwanted cache eviction.</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc</span><br><span>index c744e47..2399bec 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc</span><br><span>@@ -1063,7 +1063,7 @@</span><br><span> mov $TOP_MEM2, %ecx # MSR:C001_001D</span><br><span> _WRMSR</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # setup MTTRs for stacks</span><br><span style="color: hsl(120, 100%, 40%);">+ # setup MTRRs for stacks</span><br><span> # A speculative read can be generated by a speculative fetch mis-aligned in a code zone</span><br><span> # or due to a data zone being interpreted as code. When a speculative read occurs outside a</span><br><span> # controlled region (intentionally used by software), it could cause an unwanted cache eviction.</span><br><span>diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc</span><br><span>index 5a4f7b9..7e12db1 100644</span><br><span>--- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc</span><br><span>+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc</span><br><span>@@ -1063,7 +1063,7 @@</span><br><span> mov $TOP_MEM2, %ecx # MSR:C001_001D</span><br><span> _WRMSR</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- # setup MTTRs for stacks</span><br><span style="color: hsl(120, 100%, 40%);">+ # setup MTRRs for stacks</span><br><span> # A speculative read can be generated by a speculative fetch mis-aligned in a code zone</span><br><span> # or due to a data zone being interpreted as code. When a speculative read occurs outside a</span><br><span> # controlled region (intentionally used by software), it could cause an unwanted cache eviction.</span><br><span>diff --git a/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h b/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h</span><br><span>index ef9970d..fb3e6ba 100644</span><br><span>--- a/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h</span><br><span>+++ b/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h</span><br><span>@@ -47,7 +47,7 @@</span><br><span> @retval EFI_SUCCESS Mtrr are set successfully.</span><br><span> @retval EFI_LOAD_ERROR No empty MTRRs to use.</span><br><span> @retval EFI_INVALID_PARAMETER The input parameter is not valid.</span><br><span style="color: hsl(0, 100%, 40%);">- @retval others An error occurs when setting MTTR.</span><br><span style="color: hsl(120, 100%, 40%);">+ @retval others An error occurs when setting MTRR.</span><br><span> </span><br><span> **/</span><br><span> EFI_STATUS</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25568">change 25568</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74 </div>
<div style="display:none"> Gerrit-Change-Number: 25568 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer@gmx.net> </div>