[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridege: Create util.c
Richard Spiegel (Code Review)
gerrit at coreboot.org
Thu Apr 5 00:23:11 CEST 2018
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25533
Change subject: soc/amd/stoneyridege: Create util.c
......................................................................
soc/amd/stoneyridege: Create util.c
As part of moving AGESA calls from bootblock to romstage, code was created
to read and write to NB IOAPIC. This code should be generalized and made
available to anyone. Create file util.c to store the generalized code. Make
code available at bootblock, romstage, postcar, verstage, ramstage and smm.
BUG=b:74236170
TEST=Build and boot grunt.
Change-Id: I3c4d1596e0be91db2e5ebd63d33e20f4894528e6
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/Makefile.inc
M src/soc/amd/stoneyridge/bootblock/bootblock.c
M src/soc/amd/stoneyridge/include/soc/northbridge.h
M src/soc/amd/stoneyridge/romstage.c
A src/soc/amd/stoneyridge/util.c
5 files changed, 63 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/25533/1
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 61704ea..afdf679 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -48,7 +48,7 @@
bootblock-y += sb_util.c
bootblock-y += tsc_freq.c
bootblock-y += southbridge.c
-bootblock-y += sb_util.c
+bootblock-y += util.c
romstage-y += BiosCallOuts.c
romstage-y += i2c.c
@@ -66,6 +66,7 @@
romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
romstage-y += tsc_freq.c
romstage-y += southbridge.c
+romstage-y += util.c
verstage-y += gpio.c
verstage-y += i2c.c
@@ -75,11 +76,13 @@
verstage-y += reset.c
verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
verstage-y += tsc_freq.c
+verstage-y += util.c
postcar-y += monotonic_timer.c
postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
postcar-y += ramtop.c
postcar-y += sb_util.c
+postcar-y += util.c
ramstage-y += BiosCallOuts.c
ramstage-y += i2c.c
@@ -108,6 +111,7 @@
ramstage-y += tsc_freq.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-y += finalize.c
+ramstage-y += util.c
smm-y += monotonic_timer.c
smm-y += smihandler.c
@@ -116,6 +120,7 @@
smm-y += tsc_freq.c
smm-$(CONFIG_DEBUG_SMI) += uart.c
smm-$(CONFIG_SPI_FLASH) += spi.c
+smm-y += util.c
CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge
CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 8f1ac5d..404e24b 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -30,13 +30,6 @@
#include <amdblocks/psp.h>
#include <timestamp.h>
-static uintptr_t get_ap_ptr(void)
-{
- /* Use the first IOAPIC scratch register */
- pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, NB_IOAPIC_SCRATCH0);
- return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA);
-}
-
/* Set the MMIO Configuration Base Address and Bus Range. */
static void amd_initmmio(void)
{
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 6e42b39..547383d 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -30,10 +30,23 @@
/* NB IOAPIC registers */
#define NB_IOAPIC_INDEX 0xf8
#define NB_IOAPIC_DATA 0xfc
-#define NB_IOAPIC_ADDRESS 0x01
+#define NB_IOAPIC_FEATURE_CTRL 0x00
+#define NB_IOAPIC_ADDRESS_LOW 0x01
+#define NB_IOAPIC_ADDRESS_HIGH 0x02
+#define NB_IOAPIC_GBIF_IRR 0x0f
+#define NB_IOAPIC_BR0_IRR 0x10
+#define NB_IOAPIC_BR1_IRR 0x11
+#define NB_IOAPIC_BR2_IRR 0x12
+#define NB_IOAPIC_BR3_IRR 0x13
+#define NB_IOAPIC_BR4_IRR 0x14
+#define NB_IOAPIC_APG_IRR 0x2f
+#define NB_IOAPIC_SPG_IRR 0x30
+#define NB_IOAPIC_SER_IRQ_IRR 0x31
#define NB_IOAPIC_SCRATCH0 0x3e
#define NB_IOAPIC_SCRATCH1 0x3f
+#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0
+
/* D18F1 - Address Map Registers */
/* MMIO base and limit */
@@ -95,5 +108,9 @@
void domain_set_resources(device_t dev);
void fam15_finalize(void *chip_info);
void setup_uma_memory(void);
+uint32_t nb_ioapic_read(uint32_t index);
+void nb_ioapic_write(uint32_t index, uint32_t value);
+uintptr_t get_ap_ptr(void);
+void set_ap_ptr(void *entry);
#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 7911079..2b3452d 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -34,13 +34,6 @@
#include <amdblocks/psp.h>
#include <smp/node.h>
-static void set_ap_ptr(void *entry)
-{
- /* Use the first IOAPIC scratch register */
- pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, NB_IOAPIC_SCRATCH0);
- pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, (u32)entry);
-}
-
asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
diff --git a/src/soc/amd/stoneyridge/util.c b/src/soc/amd/stoneyridge/util.c
new file mode 100644
index 0000000..302bc3f
--- /dev/null
+++ b/src/soc/amd/stoneyridge/util.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Advanced Micro Devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/northbridge.h>
+#include <soc/pci_devs.h>
+
+uint32_t nb_ioapic_read(uint32_t index)
+{
+ pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
+ return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA);
+}
+
+void nb_ioapic_write(uint32_t index, uint32_t value)
+{
+ pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);
+ pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value);
+}
+
+uintptr_t get_ap_ptr(void)
+{
+ return nb_ioapic_read(AP_SCRATCH_REG);
+}
+
+void set_ap_ptr(void *entry)
+{
+ nb_ioapic_write(AP_SCRATCH_REG, (u32)entry);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3c4d1596e0be91db2e5ebd63d33e20f4894528e6
Gerrit-Change-Number: 25533
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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