<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25533">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridege: Create util.c<br><br>As part of moving AGESA calls from bootblock to romstage, code was created<br>to read and write to NB IOAPIC. This code should be generalized and made<br>available to anyone. Create file util.c to store the generalized code. Make<br>code available at bootblock, romstage, postcar, verstage, ramstage and smm.<br><br>BUG=b:74236170<br>TEST=Build and boot grunt.<br><br>Change-Id: I3c4d1596e0be91db2e5ebd63d33e20f4894528e6<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/Makefile.inc<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>M src/soc/amd/stoneyridge/include/soc/northbridge.h<br>M src/soc/amd/stoneyridge/romstage.c<br>A src/soc/amd/stoneyridge/util.c<br>5 files changed, 63 insertions(+), 16 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/25533/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc</span><br><span>index 61704ea..afdf679 100644</span><br><span>--- a/src/soc/amd/stoneyridge/Makefile.inc</span><br><span>+++ b/src/soc/amd/stoneyridge/Makefile.inc</span><br><span>@@ -48,7 +48,7 @@</span><br><span> bootblock-y += sb_util.c</span><br><span> bootblock-y += tsc_freq.c</span><br><span> bootblock-y += southbridge.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += sb_util.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += util.c</span><br><span> </span><br><span> romstage-y += BiosCallOuts.c</span><br><span> romstage-y += i2c.c</span><br><span>@@ -66,6 +66,7 @@</span><br><span> romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c</span><br><span> romstage-y += tsc_freq.c</span><br><span> romstage-y += southbridge.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += util.c</span><br><span> </span><br><span> verstage-y += gpio.c</span><br><span> verstage-y += i2c.c</span><br><span>@@ -75,11 +76,13 @@</span><br><span> verstage-y += reset.c</span><br><span> verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c</span><br><span> verstage-y += tsc_freq.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += util.c</span><br><span> </span><br><span> postcar-y += monotonic_timer.c</span><br><span> postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c</span><br><span> postcar-y += ramtop.c</span><br><span> postcar-y += sb_util.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += util.c</span><br><span> </span><br><span> ramstage-y += BiosCallOuts.c</span><br><span> ramstage-y += i2c.c</span><br><span>@@ -108,6 +111,7 @@</span><br><span> ramstage-y += tsc_freq.c</span><br><span> ramstage-$(CONFIG_SPI_FLASH) += spi.c</span><br><span> ramstage-y += finalize.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += util.c</span><br><span> </span><br><span> smm-y += monotonic_timer.c</span><br><span> smm-y += smihandler.c</span><br><span>@@ -116,6 +120,7 @@</span><br><span> smm-y += tsc_freq.c</span><br><span> smm-$(CONFIG_DEBUG_SMI) += uart.c</span><br><span> smm-$(CONFIG_SPI_FLASH) += spi.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-y += util.c</span><br><span> </span><br><span> CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge</span><br><span> CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include</span><br><span>diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>index 8f1ac5d..404e24b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c</span><br><span>@@ -30,13 +30,6 @@</span><br><span> #include <amdblocks/psp.h></span><br><span> #include <timestamp.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static uintptr_t get_ap_ptr(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Use the first IOAPIC scratch register */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, NB_IOAPIC_SCRATCH0);</span><br><span style="color: hsl(0, 100%, 40%);">- return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Set the MMIO Configuration Base Address and Bus Range. */</span><br><span> static void amd_initmmio(void)</span><br><span> {</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>index 6e42b39..547383d 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>@@ -30,10 +30,23 @@</span><br><span> /* NB IOAPIC registers */</span><br><span> #define NB_IOAPIC_INDEX 0xf8</span><br><span> #define NB_IOAPIC_DATA 0xfc</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_ADDRESS 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_FEATURE_CTRL 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_ADDRESS_LOW 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_ADDRESS_HIGH 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_GBIF_IRR 0x0f</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_BR0_IRR 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_BR1_IRR 0x11</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_BR2_IRR 0x12</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_BR3_IRR 0x13</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_BR4_IRR 0x14</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_APG_IRR 0x2f</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_SPG_IRR 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_SER_IRQ_IRR 0x31</span><br><span> #define NB_IOAPIC_SCRATCH0 0x3e</span><br><span> #define NB_IOAPIC_SCRATCH1 0x3f</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* D18F1 - Address Map Registers */</span><br><span> </span><br><span> /* MMIO base and limit */</span><br><span>@@ -95,5 +108,9 @@</span><br><span> void domain_set_resources(device_t dev);</span><br><span> void fam15_finalize(void *chip_info);</span><br><span> void setup_uma_memory(void);</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t nb_ioapic_read(uint32_t index);</span><br><span style="color: hsl(120, 100%, 40%);">+void nb_ioapic_write(uint32_t index, uint32_t value);</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t get_ap_ptr(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void set_ap_ptr(void *entry);</span><br><span> </span><br><span> #endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */</span><br><span>diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c</span><br><span>index 7911079..2b3452d 100644</span><br><span>--- a/src/soc/amd/stoneyridge/romstage.c</span><br><span>+++ b/src/soc/amd/stoneyridge/romstage.c</span><br><span>@@ -34,13 +34,6 @@</span><br><span> #include <amdblocks/psp.h></span><br><span> #include <smp/node.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_ap_ptr(void *entry)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Use the first IOAPIC scratch register */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, NB_IOAPIC_SCRATCH0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, (u32)entry);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> asmlinkage void car_stage_entry(void)</span><br><span> {</span><br><span> struct postcar_frame pcf;</span><br><span>diff --git a/src/soc/amd/stoneyridge/util.c b/src/soc/amd/stoneyridge/util.c</span><br><span>new file mode 100644</span><br><span>index 0000000..302bc3f</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/amd/stoneyridge/util.c</span><br><span>@@ -0,0 +1,39 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Advanced Micro Devices</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/northbridge.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t nb_ioapic_read(uint32_t index)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);</span><br><span style="color: hsl(120, 100%, 40%);">+ return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void nb_ioapic_write(uint32_t index, uint32_t value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t get_ap_ptr(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return nb_ioapic_read(AP_SCRATCH_REG);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void set_ap_ptr(void *entry)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ nb_ioapic_write(AP_SCRATCH_REG, (u32)entry);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25533">change 25533</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3c4d1596e0be91db2e5ebd63d33e20f4894528e6 </div>
<div style="display:none"> Gerrit-Change-Number: 25533 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>