[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Enable early mmc CMD0, CMD1 for GLK
Bora Guvendik (Code Review)
gerrit at coreboot.org
Tue Apr 3 23:36:40 CEST 2018
Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/25514
Change subject: soc/intel/apollolake: Enable early mmc CMD0, CMD1 for GLK
......................................................................
soc/intel/apollolake: Enable early mmc CMD0, CMD1 for GLK
In order to improve boot time via emmc, enable Intel common
code that sends CMD0 and CMD1 early in firmware.
Change-Id: Ib4e791607059d12b3f5692f6404cb9eb39d79f6d
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/Makefile.inc
A src/soc/intel/apollolake/early_mmc.c
M src/soc/intel/apollolake/include/soc/iomap.h
M src/soc/intel/apollolake/romstage.c
5 files changed, 75 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/25514/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index fcb1ef7..4ff3369 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -10,6 +10,7 @@
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_SGX
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
+ select SOC_INTEL_COMMON_EARLY_MMC_WAKE
help
Intel GLK support
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 65df559..f1b056d 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -90,6 +90,7 @@
romstage-y += gpio_glk.c
smm-y += gpio_glk.c
ramstage-y += gpio_glk.c
+romstage-y += early_mmc.c
else
bootblock-y += gpio_apl.c
romstage-y += gpio_apl.c
diff --git a/src/soc/intel/apollolake/early_mmc.c b/src/soc/intel/apollolake/early_mmc.c
new file mode 100644
index 0000000..9761da0
--- /dev/null
+++ b/src/soc/intel/apollolake/early_mmc.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "chip.h"
+#include <intelblocks/early_mmc.h>
+#include <intelblocks/gpio.h>
+#include <soc/pci_devs.h>
+
+
+static const struct pad_config mmc_early_gpios[] = {
+ PAD_CFG_NF_IOSSTATE(GPIO_211, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC_RST_B*/
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_104, UP_20K, DEEP, NF1),/*EMMC_DNX_PWR_EN_B*/
+ PAD_CFG_NF_IOSSTATE(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0),/*EMMC0_CLK*/
+ PAD_CFG_NF(GPIO_199, DN_20K, DEEP, NF1),/*EMMC0_CLK_FB*/
+ PAD_CFG_NF_IOSSTATE(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D0*/
+ PAD_CFG_NF_IOSSTATE(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D1*/
+ PAD_CFG_NF_IOSSTATE(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D2*/
+ PAD_CFG_NF_IOSSTATE(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D3*/
+ PAD_CFG_NF_IOSSTATE(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D4*/
+ PAD_CFG_NF_IOSSTATE(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D5*/
+ PAD_CFG_NF_IOSSTATE(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D6*/
+ PAD_CFG_NF_IOSSTATE(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_D7*/
+ PAD_CFG_NF_IOSSTATE(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1),/*EMMC0_CMD*/
+ PAD_CFG_NF_IOSSTATE(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0)/*EMMC0_STROBE*/
+};
+
+int soc_set_mmc_gpios(void)
+{
+ gpio_configure_pads(&mmc_early_gpios[0], ARRAY_SIZE(mmc_early_gpios));
+
+ return 0;
+}
+
+void soc_get_mmc_frequencies(uint32_t* f_min, uint32_t* f_max)
+{
+ *f_min = 400000;
+ *f_max = 25000000;
+}
+
+int soc_set_mmc_dll(struct mmc_dll_params* params)
+{
+ const struct device *dev = SA_DEV_ROOT;
+ const struct soc_intel_apollolake_config *config = dev->chip_info;
+
+ params->emmc_tx_data_cntl1 = config->emmc_tx_data_cntl1;
+ params->emmc_tx_data_cntl2 = config->emmc_tx_data_cntl2;
+ params->emmc_rx_cmd_data_cntl1 = config->emmc_rx_cmd_data_cntl1;
+ params->emmc_rx_cmd_data_cntl2 = config->emmc_rx_cmd_data_cntl2;
+ params->emmc_rx_strobe_cntl = config->emmc_rx_strobe_cntl;
+ params->emmc_tx_cmd_cntl = config->emmc_tx_cmd_cntl;
+
+ return 0;
+}
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 7e6a795..a912c3b 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -49,6 +49,7 @@
/* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */
#define PRERAM_SPI_BASE_ADDRESS 0xfe010000
#define EARLY_GSPI_BASE_ADDRESS 0xfe011000
+#define PRERAM_MMC_BASE_ADDRESS 0xfe030000
/* Temporary BAR for early I2C bus access */
#define PRERAM_I2C_BASE_ADDRESS(x) (0xfe020000 + (0x1000 * (x)))
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index a8a0dd1..77f4af4 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -52,6 +52,7 @@
#include <delay.h>
#include <compiler.h>
#include "chip.h"
+#include <intelblocks/early_mmc.h>
static const uint8_t hob_variable_guid[16] = {
0x7d, 0x14, 0x34, 0xa0, 0x0c, 0x69, 0x54, 0x41,
@@ -198,6 +199,11 @@
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake);
+ if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE)) {
+ if (early_mmc_wake_hw() < 0)
+ printk(BIOS_DEBUG, "Early mmc initilization failed \n");
+ }
+
if (punit_init())
set_max_freq();
else
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib4e791607059d12b3f5692f6404cb9eb39d79f6d
Gerrit-Change-Number: 25514
Gerrit-PatchSet: 1
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
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