[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Move pm/smi_read/write functions to util file
Marshall Dawson (Code Review)
gerrit at coreboot.org
Fri Sep 29 02:13:30 CEST 2017
Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21759
Change subject: amd/stoneyridge: Move pm/smi_read/write functions to util file
......................................................................
amd/stoneyridge: Move pm/smi_read/write functions to util file
Pull all pm_read and write, smi_read and write variants into a single
file.
Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/Makefile.inc
M src/soc/amd/stoneyridge/include/soc/smi.h
M src/soc/amd/stoneyridge/include/soc/southbridge.h
A src/soc/amd/stoneyridge/sb_util.c
M src/soc/amd/stoneyridge/smi.c
M src/soc/amd/stoneyridge/smi_util.c
M src/soc/amd/stoneyridge/southbridge.c
7 files changed, 77 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/21759/1
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 28b3244..daab687 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -74,6 +74,7 @@
ramstage-y += gpio.c
ramstage-y += hda.c
ramstage-y += southbridge.c
+ramstage-y += sb_util.c
ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
ramstage-y += lpc.c
ramstage-y += model_15_init.c
@@ -92,6 +93,7 @@
smm-y += smihandler.c
smm-y += smi_util.c
+smm-y += sb_util.c
smm-y += tsc_freq.c
smm-y += uart.c
diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h
index 2a0748c..daf7a0c 100644
--- a/src/soc/amd/stoneyridge/include/soc/smi.h
+++ b/src/soc/amd/stoneyridge/include/soc/smi.h
@@ -19,9 +19,6 @@
#include <arch/io.h>
-/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it. */
-#define SMI_BASE 0xfed80200
-
#define SMI_SCI_STATUS 0x10
/* SMI source and status */
@@ -195,26 +192,6 @@
SMI_LVL_LOW = 0,
SMI_LVL_HIGH = 1,
};
-
-static inline uint32_t smi_read32(uint8_t offset)
-{
- return read32((void *)(SMI_BASE + offset));
-}
-
-static inline void smi_write32(uint8_t offset, uint32_t value)
-{
- write32((void *)(SMI_BASE + offset), value);
-}
-
-static inline uint16_t smi_read16(uint8_t offset)
-{
- return read16((void *)(SMI_BASE + offset));
-}
-
-static inline void smi_write16(uint8_t offset, uint16_t value)
-{
- write16((void *)(SMI_BASE + offset), value);
-}
void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
void disable_gevent_smi(uint8_t gevent);
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 7393abc..80fcf87 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -25,10 +25,9 @@
#define IO_APIC2_ADDR 0xfec20000
-/* Offsets from ACPI_MMIO_BASE
- * This is defined by AGESA, but we don't include AGESA headers to avoid
- * polluting the namespace.
- */
+/* Offsets from ACPI_MMIO_BASE */
+#define APU_SMI_BASE 0xfed80200
+
#define PM_MMIO_BASE 0xfed80300
#define APU_UART0_BASE 0xfedc6000
@@ -194,6 +193,10 @@
void pm_write8(u8 reg, u8 value);
void pm_write16(u8 reg, u16 value);
void pm_write32(u8 reg, u32 value);
+u16 smi_read16(u8 reg);
+u32 smi_read32(u8 reg);
+void smi_write16(u8 reg, u16 value);
+void smi_write32(u8 reg, u32 value);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
void s3_resume_init_data(void *FchParams);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c
new file mode 100644
index 0000000..87bff70
--- /dev/null
+++ b/src/soc/amd/stoneyridge/sb_util.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/southbridge.h>
+
+void pm_write8(u8 reg, u8 value)
+{
+ write8((void *)(PM_MMIO_BASE + reg), value);
+}
+
+u8 pm_read8(u8 reg)
+{
+ return read8((void *)(PM_MMIO_BASE + reg));
+}
+
+void pm_write16(u8 reg, u16 value)
+{
+ write16((void *)(PM_MMIO_BASE + reg), value);
+}
+
+u16 pm_read16(u8 reg)
+{
+ return read16((void *)(PM_MMIO_BASE + reg));
+}
+
+void pm_write32(u8 reg, u32 value)
+{
+ write32((void *)(PM_MMIO_BASE + reg), value);
+}
+
+u32 pm_read32(u8 reg)
+{
+ return read32((void *)(PM_MMIO_BASE + reg));
+}
+
+void smi_write32(uint8_t offset, uint32_t value)
+{
+ write32((void *)(APU_SMI_BASE + offset), value);
+}
+
+uint32_t smi_read32(uint8_t offset)
+{
+ return read32((void *)(APU_SMI_BASE + offset));
+}
+
+uint16_t smi_read16(uint8_t offset)
+{
+ return read16((void *)(APU_SMI_BASE + offset));
+}
+
+void smi_write16(uint8_t offset, uint16_t value)
+{
+ write16((void *)(APU_SMI_BASE + offset), value);
+}
diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c
index 31ca5d1..1cfbc03 100644
--- a/src/soc/amd/stoneyridge/smi.c
+++ b/src/soc/amd/stoneyridge/smi.c
@@ -9,6 +9,7 @@
#include <console/console.h>
#include <cpu/cpu.h>
+#include <soc/southbridge.h>
#include <soc/smi.h>
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c
index 68e792c..42d651a 100644
--- a/src/soc/amd/stoneyridge/smi_util.c
+++ b/src/soc/amd/stoneyridge/smi_util.c
@@ -6,6 +6,7 @@
*/
#include <console/console.h>
+#include <soc/southbridge.h>
#include <soc/smi.h>
static void configure_smi(uint8_t smi_num, uint8_t mode)
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index a829575..fca8041 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -40,36 +40,6 @@
return (int)tmp;
}
-void pm_write8(u8 reg, u8 value)
-{
- write8((void *)(PM_MMIO_BASE + reg), value);
-}
-
-u8 pm_read8(u8 reg)
-{
- return read8((void *)(PM_MMIO_BASE + reg));
-}
-
-void pm_write16(u8 reg, u16 value)
-{
- write16((void *)(PM_MMIO_BASE + reg), value);
-}
-
-u16 pm_read16(u8 reg)
-{
- return read16((void *)(PM_MMIO_BASE + reg));
-}
-
-void pm_write32(u8 reg, u32 value)
-{
- write32((void *)(PM_MMIO_BASE + reg), value);
-}
-
-u32 pm_read32(u8 reg)
-{
- return read32((void *)(PM_MMIO_BASE + reg));
-}
-
void sb_enable(device_t dev)
{
printk(BIOS_DEBUG, "%s\n", __func__);
--
To view, visit https://review.coreboot.org/21759
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772
Gerrit-Change-Number: 21759
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20170929/e2067692/attachment-0001.html>
More information about the coreboot-gerrit
mailing list