<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21759">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Move pm/smi_read/write functions to util file<br><br>Pull all pm_read and write, smi_read and write variants into a single<br>file.<br><br>Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/Makefile.inc<br>M src/soc/amd/stoneyridge/include/soc/smi.h<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>A src/soc/amd/stoneyridge/sb_util.c<br>M src/soc/amd/stoneyridge/smi.c<br>M src/soc/amd/stoneyridge/smi_util.c<br>M src/soc/amd/stoneyridge/southbridge.c<br>7 files changed, 77 insertions(+), 57 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/21759/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc<br>index 28b3244..daab687 100644<br>--- a/src/soc/amd/stoneyridge/Makefile.inc<br>+++ b/src/soc/amd/stoneyridge/Makefile.inc<br>@@ -74,6 +74,7 @@<br> ramstage-y += gpio.c<br> ramstage-y += hda.c<br> ramstage-y += southbridge.c<br>+ramstage-y += sb_util.c<br> ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c<br> ramstage-y += lpc.c<br> ramstage-y += model_15_init.c<br>@@ -92,6 +93,7 @@<br> <br> smm-y += smihandler.c<br> smm-y += smi_util.c<br>+smm-y += sb_util.c<br> smm-y += tsc_freq.c<br> smm-y += uart.c<br> <br>diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h<br>index 2a0748c..daf7a0c 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/smi.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/smi.h<br>@@ -19,9 +19,6 @@<br> <br> #include <arch/io.h><br> <br>-/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it. */<br>-#define SMI_BASE 0xfed80200<br>-<br> #define SMI_SCI_STATUS 0x10<br> <br> /* SMI source and status */<br>@@ -195,26 +192,6 @@<br> SMI_LVL_LOW = 0,<br> SMI_LVL_HIGH = 1,<br> };<br>-<br>-static inline uint32_t smi_read32(uint8_t offset)<br>-{<br>- return read32((void *)(SMI_BASE + offset));<br>-}<br>-<br>-static inline void smi_write32(uint8_t offset, uint32_t value)<br>-{<br>- write32((void *)(SMI_BASE + offset), value);<br>-}<br>-<br>-static inline uint16_t smi_read16(uint8_t offset)<br>-{<br>- return read16((void *)(SMI_BASE + offset));<br>-}<br>-<br>-static inline void smi_write16(uint8_t offset, uint16_t value)<br>-{<br>- write16((void *)(SMI_BASE + offset), value);<br>-}<br> <br> void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);<br> void disable_gevent_smi(uint8_t gevent);<br>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>index 7393abc..80fcf87 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>@@ -25,10 +25,9 @@<br> <br> #define IO_APIC2_ADDR 0xfec20000<br> <br>-/* Offsets from ACPI_MMIO_BASE<br>- * This is defined by AGESA, but we don't include AGESA headers to avoid<br>- * polluting the namespace.<br>- */<br>+/* Offsets from ACPI_MMIO_BASE */<br>+#define APU_SMI_BASE 0xfed80200<br>+<br> #define PM_MMIO_BASE 0xfed80300<br> <br> #define APU_UART0_BASE 0xfedc6000<br>@@ -194,6 +193,10 @@<br> void pm_write8(u8 reg, u8 value);<br> void pm_write16(u8 reg, u16 value);<br> void pm_write32(u8 reg, u32 value);<br>+u16 smi_read16(u8 reg);<br>+u32 smi_read32(u8 reg);<br>+void smi_write16(u8 reg, u16 value);<br>+void smi_write32(u8 reg, u32 value);<br> int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);<br> void s3_resume_init_data(void *FchParams);<br> int s3_save_nvram_early(u32 dword, int size, int nvram_pos);<br>diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c<br>new file mode 100644<br>index 0000000..87bff70<br>--- /dev/null<br>+++ b/src/soc/amd/stoneyridge/sb_util.c<br>@@ -0,0 +1,66 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <soc/southbridge.h><br>+<br>+void pm_write8(u8 reg, u8 value)<br>+{<br>+ write8((void *)(PM_MMIO_BASE + reg), value);<br>+}<br>+<br>+u8 pm_read8(u8 reg)<br>+{<br>+ return read8((void *)(PM_MMIO_BASE + reg));<br>+}<br>+<br>+void pm_write16(u8 reg, u16 value)<br>+{<br>+ write16((void *)(PM_MMIO_BASE + reg), value);<br>+}<br>+<br>+u16 pm_read16(u8 reg)<br>+{<br>+ return read16((void *)(PM_MMIO_BASE + reg));<br>+}<br>+<br>+void pm_write32(u8 reg, u32 value)<br>+{<br>+ write32((void *)(PM_MMIO_BASE + reg), value);<br>+}<br>+<br>+u32 pm_read32(u8 reg)<br>+{<br>+ return read32((void *)(PM_MMIO_BASE + reg));<br>+}<br>+<br>+void smi_write32(uint8_t offset, uint32_t value)<br>+{<br>+ write32((void *)(APU_SMI_BASE + offset), value);<br>+}<br>+<br>+uint32_t smi_read32(uint8_t offset)<br>+{<br>+ return read32((void *)(APU_SMI_BASE + offset));<br>+}<br>+<br>+uint16_t smi_read16(uint8_t offset)<br>+{<br>+ return read16((void *)(APU_SMI_BASE + offset));<br>+}<br>+<br>+void smi_write16(uint8_t offset, uint16_t value)<br>+{<br>+ write16((void *)(APU_SMI_BASE + offset), value);<br>+}<br>diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c<br>index 31ca5d1..1cfbc03 100644<br>--- a/src/soc/amd/stoneyridge/smi.c<br>+++ b/src/soc/amd/stoneyridge/smi.c<br>@@ -9,6 +9,7 @@<br> <br> #include <console/console.h><br> #include <cpu/cpu.h><br>+#include <soc/southbridge.h><br> #include <soc/smi.h><br> <br> void smm_setup_structures(void *gnvs, void *tcg, void *smi1)<br>diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c<br>index 68e792c..42d651a 100644<br>--- a/src/soc/amd/stoneyridge/smi_util.c<br>+++ b/src/soc/amd/stoneyridge/smi_util.c<br>@@ -6,6 +6,7 @@<br> */<br> <br> #include <console/console.h><br>+#include <soc/southbridge.h><br> #include <soc/smi.h><br> <br> static void configure_smi(uint8_t smi_num, uint8_t mode)<br>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c<br>index a829575..fca8041 100644<br>--- a/src/soc/amd/stoneyridge/southbridge.c<br>+++ b/src/soc/amd/stoneyridge/southbridge.c<br>@@ -40,36 +40,6 @@<br> return (int)tmp;<br> }<br> <br>-void pm_write8(u8 reg, u8 value)<br>-{<br>- write8((void *)(PM_MMIO_BASE + reg), value);<br>-}<br>-<br>-u8 pm_read8(u8 reg)<br>-{<br>- return read8((void *)(PM_MMIO_BASE + reg));<br>-}<br>-<br>-void pm_write16(u8 reg, u16 value)<br>-{<br>- write16((void *)(PM_MMIO_BASE + reg), value);<br>-}<br>-<br>-u16 pm_read16(u8 reg)<br>-{<br>- return read16((void *)(PM_MMIO_BASE + reg));<br>-}<br>-<br>-void pm_write32(u8 reg, u32 value)<br>-{<br>- write32((void *)(PM_MMIO_BASE + reg), value);<br>-}<br>-<br>-u32 pm_read32(u8 reg)<br>-{<br>- return read32((void *)(PM_MMIO_BASE + reg));<br>-}<br>-<br> void sb_enable(device_t dev)<br> {<br> printk(BIOS_DEBUG, "%s\n", __func__);<br></pre><p>To view, visit <a href="https://review.coreboot.org/21759">change 21759</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21759"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772 </div>
<div style="display:none"> Gerrit-Change-Number: 21759 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>