[coreboot-gerrit] Change in coreboot[master]: WIP amd/stoneridge: Enable SMI trap on SlpTyp
Marshall Dawson (Code Review)
gerrit at coreboot.org
Thu Sep 28 18:28:19 CEST 2017
Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21752
Change subject: WIP amd/stoneridge: Enable SMI trap on SlpTyp
......................................................................
WIP amd/stoneridge: Enable SMI trap on SlpTyp
Consider adding a check for HAVE_ACPI_RESUME, maybe SOC_AMD_COMMON_BLOCK_PSP.
Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/southbridge.c
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/21752/1
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index b5357a9..4c91efa 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -89,8 +89,17 @@
pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ /* APMC - SMI Command Port */
pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
+
+ /* SlpTypEn */
+ pm_write32(PM_PCI_CTRL,
+ (pm_read32(PM_PCI_CTRL) | FORCE_SLPSTATE_RETRY)
+ & ~FORCE_STPCLK_RETRY);
+ pm_write32(PM_RST_CTRL1,
+ pm_read32(PM_RST_CTRL1) & ~SLPTYPE_CONTROL_EN);
+ configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI);
} else {
pm_write16(PM_ACPI_SMI_CMD, 0);
}
--
To view, visit https://review.coreboot.org/21752
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229
Gerrit-Change-Number: 21752
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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