[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add config option of CpuRatio

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21709


Change subject: soc/intel/cannonlake: Add config option of CpuRatio
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soc/intel/cannonlake: Add config option of CpuRatio

Add config option of CPU ratio as input to Fsp Memory init.

Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/romstage/romstage.c
2 files changed, 4 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/21709/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 5a4dfd3..49b6140 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -227,6 +227,9 @@
 	 * PchSerialIoHidden
 	 */
 	uint8_t SerialIoDevMode[PchSerialIoIndexMAX];
+	/* Valid Range 0 to 63. CPU Ratio is 0 when disabled */
+	uint8_t cpuratio;
+
 };
 
 typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index a9ad1d8..9e95b47 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -86,6 +86,7 @@
 	m_cfg->PcieRpEnableMask = mask;
 	m_cfg->PrmrrSize = config->PrmrrSize;
 	m_cfg->EnableC6Dram = config->enable_c6dram;
+	m_cfg->CpuRatio = config->cpuratio;
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b
Gerrit-Change-Number: 21709
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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