<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21709">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add config option of CpuRatio<br><br>Add config option of CPU ratio as input to Fsp Memory init.<br><br>Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/chip.h<br>M src/soc/intel/cannonlake/romstage/romstage.c<br>2 files changed, 4 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/21709/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h<br>index 5a4dfd3..49b6140 100644<br>--- a/src/soc/intel/cannonlake/chip.h<br>+++ b/src/soc/intel/cannonlake/chip.h<br>@@ -227,6 +227,9 @@<br>      * PchSerialIoHidden<br>   */<br>   uint8_t SerialIoDevMode[PchSerialIoIndexMAX];<br>+        /* Valid Range 0 to 63. CPU Ratio is 0 when disabled */<br>+      uint8_t cpuratio;<br>+<br> };<br> <br> typedef struct soc_intel_cannonlake_config config_t;<br>diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c<br>index a9ad1d8..9e95b47 100644<br>--- a/src/soc/intel/cannonlake/romstage/romstage.c<br>+++ b/src/soc/intel/cannonlake/romstage/romstage.c<br>@@ -86,6 +86,7 @@<br>       m_cfg->PcieRpEnableMask = mask;<br>    m_cfg->PrmrrSize = config->PrmrrSize;<br>   m_cfg->EnableC6Dram = config->enable_c6dram;<br>+   m_cfg->CpuRatio = config->cpuratio;<br> }<br> <br> void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)<br></pre><p>To view, visit <a href="https://review.coreboot.org/21709">change 21709</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21709"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b </div>
<div style="display:none"> Gerrit-Change-Number: 21709 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>