[coreboot-gerrit] Change in coreboot[master]: nb/intel/x4x: Change memory layout to improve MTRR
Arthur Heymans (Code Review)
gerrit at coreboot.org
Fri Sep 22 12:31:13 CEST 2017
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21634
Change subject: nb/intel/x4x: Change memory layout to improve MTRR
......................................................................
nb/intel/x4x: Change memory layout to improve MTRR
This change also makes sure that the sum the uma regions (TSEG, GSM,
GSM) is 4MiB aligned. This is needed to avoid cbmem_top floating between
2 usable ram region, since cbmem_top is aligned 4MiB down to easy MTRR
setup for ramstage. At least tianocore requires this and fails to boot
without it.
Better MTRR are achieved by making the memory 'hole' till 4GiB exactly
2Gib.
This code mimics how it is done in nb/intel/gm45 and achieves similar
results.
TESTED on Intel DG43GT.
Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout
M src/mainboard/intel/dg43gt/cmos.layout
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/intel/x4x/northbridge.c
M src/northbridge/intel/x4x/raminit_ddr2.c
5 files changed, 24 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/21634/1
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout
index fac9d35..89d328e 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout
@@ -100,7 +100,6 @@
7 0 Disable
7 1 Enable
7 2 Keep
-11 0 1M
11 1 4M
11 2 8M
11 3 16M
diff --git a/src/mainboard/intel/dg43gt/cmos.layout b/src/mainboard/intel/dg43gt/cmos.layout
index e5e2a97..f883955 100644
--- a/src/mainboard/intel/dg43gt/cmos.layout
+++ b/src/mainboard/intel/dg43gt/cmos.layout
@@ -102,7 +102,6 @@
7 2 Keep
10 0 AHCI
10 1 Compatible
-11 0 1M
11 1 4M
11 2 8M
11 3 16M
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index 27fe916..fd6a9f7 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -67,7 +67,11 @@
get_option(&gfxsize, "gfx_uma_size");
if (gfxsize > 12)
gfxsize = 6;
- pci_write_config16(d0f0, D0F0_GGC, 0x0100 | (gfxsize + 1) << 4);
+ /* Need at least 4M for cbmem_top alignment */
+ else if (gfxsize < 1)
+ gfxsize = 1;
+ /* Set GTT size to 1+1M */
+ pci_write_config16(d0f0, D0F0_GGC, 0x0900 | (gfxsize + 1) << 4);
} else { /* Does not feature internal graphics */
pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN);
pci_write_config16(d0f0, D0F0_GGC, (1 << 1));
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 6ba45fe..6ab2628 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -35,7 +35,7 @@
{
u8 index, reg8;
u64 tom, touud;
- u32 tomk, tseg_sizek = 0, tolud;
+ u32 tomk, tseg_sizek = 0, tolud, usable_tomk;
u32 pcie_config_base, pcie_config_size;
u32 uma_sizek = 0;
@@ -95,6 +95,9 @@
}
uma_sizek += tseg_sizek;
tomk -= tseg_sizek;
+ usable_tomk = ALIGN_DOWN(tomk, 64 << 10);
+ if (tomk - usable_tomk < (16 << 10))
+ tomk = usable_tomk;
printk(BIOS_DEBUG, "%dM\n", tseg_sizek >> 10);
@@ -121,7 +124,7 @@
printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x "
"size=0x%08x\n", tomk << 10, uma_sizek << 10);
- uma_resource(dev, index++, tomk, uma_sizek);
+ fixed_mem_resource(dev, index++, tomk, uma_sizek, IORESOURCE_RESERVE);
/* Reserve high memory where the NB BARs are up to 4GiB */
fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10,
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index 02c7fee..1aefc2e 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -1386,18 +1386,26 @@
bool reclaim;
u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud;
u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit;
+ u32 mmiostart, umasizem;
u16 ggc;
u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96,
160, 224, 352 };
u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
+ u8 reg8;
ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
gfxsize = ggc2uma[(ggc & 0xf0) >> 4];
gttsize = ggc2gtt[(ggc & 0xf00) >> 8];
- tsegsize = 1; // 1MB TSEG
+ tsegsize = 2; // 2MB TSEG
mmiosize = 0x800; // 2GB MMIO
+ umasizem = gfxsize + gttsize + tsegsize;
+ /* Further reduce MTRR usage if it costs use less than
+ 16 MiB. */
+ if (ALIGN_UP(umasizem, 64) - umasizem <= 16)
+ umasizem = ALIGN_UP(umasizem, 64);
+ mmiostart = 0x1000 - mmiosize + umasizem;
tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB;
- tolud = MIN(0x1000 - mmiosize, tom);
+ tolud = MIN(mmiostart, tom);
reclaim = false;
if ((tom - tolud) > 0x40)
@@ -1429,6 +1437,10 @@
pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud);
pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20);
pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20);
+ /* Set tseg size */
+ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
+ reg8 &= ~(3 << 1);
+ pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8 | (1 << 1));
pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20);
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad
Gerrit-Change-Number: 21634
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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