<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21634">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/x4x: Change memory layout to improve MTRR<br><br>This change also makes sure that the sum the uma regions (TSEG, GSM,<br>GSM) is 4MiB aligned. This is needed to avoid cbmem_top floating between<br>2 usable ram region, since cbmem_top is aligned 4MiB down to easy MTRR<br>setup for ramstage. At least tianocore requires this and fails to boot<br>without it.<br><br>Better MTRR are achieved by making the memory 'hole' till 4GiB exactly<br>2Gib.<br><br>This code mimics how it is done in nb/intel/gm45 and achieves similar<br>results.<br><br>TESTED on Intel DG43GT.<br><br>Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout<br>M src/mainboard/intel/dg43gt/cmos.layout<br>M src/northbridge/intel/x4x/early_init.c<br>M src/northbridge/intel/x4x/northbridge.c<br>M src/northbridge/intel/x4x/raminit_ddr2.c<br>5 files changed, 24 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/21634/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout<br>index fac9d35..89d328e 100644<br>--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout<br>+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout<br>@@ -100,7 +100,6 @@<br> 7 0 Disable<br> 7 1 Enable<br> 7 2 Keep<br>-11 0 1M<br> 11 1 4M<br> 11 2 8M<br> 11 3 16M<br>diff --git a/src/mainboard/intel/dg43gt/cmos.layout b/src/mainboard/intel/dg43gt/cmos.layout<br>index e5e2a97..f883955 100644<br>--- a/src/mainboard/intel/dg43gt/cmos.layout<br>+++ b/src/mainboard/intel/dg43gt/cmos.layout<br>@@ -102,7 +102,6 @@<br> 7 2 Keep<br> 10 0 AHCI<br> 10 1 Compatible<br>-11 0 1M<br> 11 1 4M<br> 11 2 8M<br> 11 3 16M<br>diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c<br>index 27fe916..fd6a9f7 100644<br>--- a/src/northbridge/intel/x4x/early_init.c<br>+++ b/src/northbridge/intel/x4x/early_init.c<br>@@ -67,7 +67,11 @@<br> get_option(&gfxsize, "gfx_uma_size");<br> if (gfxsize > 12)<br> gfxsize = 6;<br>- pci_write_config16(d0f0, D0F0_GGC, 0x0100 | (gfxsize + 1) << 4);<br>+ /* Need at least 4M for cbmem_top alignment */<br>+ else if (gfxsize < 1)<br>+ gfxsize = 1;<br>+ /* Set GTT size to 1+1M */<br>+ pci_write_config16(d0f0, D0F0_GGC, 0x0900 | (gfxsize + 1) << 4);<br> } else { /* Does not feature internal graphics */<br> pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN);<br> pci_write_config16(d0f0, D0F0_GGC, (1 << 1));<br>diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c<br>index 6ba45fe..6ab2628 100644<br>--- a/src/northbridge/intel/x4x/northbridge.c<br>+++ b/src/northbridge/intel/x4x/northbridge.c<br>@@ -35,7 +35,7 @@<br> {<br> u8 index, reg8;<br> u64 tom, touud;<br>- u32 tomk, tseg_sizek = 0, tolud;<br>+ u32 tomk, tseg_sizek = 0, tolud, usable_tomk;<br> u32 pcie_config_base, pcie_config_size;<br> u32 uma_sizek = 0;<br> <br>@@ -95,6 +95,9 @@<br> }<br> uma_sizek += tseg_sizek;<br> tomk -= tseg_sizek;<br>+ usable_tomk = ALIGN_DOWN(tomk, 64 << 10);<br>+ if (tomk - usable_tomk < (16 << 10))<br>+ tomk = usable_tomk;<br> <br> printk(BIOS_DEBUG, "%dM\n", tseg_sizek >> 10);<br> <br>@@ -121,7 +124,7 @@<br> <br> printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x "<br> "size=0x%08x\n", tomk << 10, uma_sizek << 10);<br>- uma_resource(dev, index++, tomk, uma_sizek);<br>+ fixed_mem_resource(dev, index++, tomk, uma_sizek, IORESOURCE_RESERVE);<br> <br> /* Reserve high memory where the NB BARs are up to 4GiB */<br> fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10,<br>diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c<br>index 02c7fee..1aefc2e 100644<br>--- a/src/northbridge/intel/x4x/raminit_ddr2.c<br>+++ b/src/northbridge/intel/x4x/raminit_ddr2.c<br>@@ -1386,18 +1386,26 @@<br> bool reclaim;<br> u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud;<br> u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit;<br>+ u32 mmiostart, umasizem;<br> u16 ggc;<br> u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96,<br> 160, 224, 352 };<br> u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};<br>+ u8 reg8;<br> <br> ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);<br> gfxsize = ggc2uma[(ggc & 0xf0) >> 4];<br> gttsize = ggc2gtt[(ggc & 0xf00) >> 8];<br>- tsegsize = 1; // 1MB TSEG<br>+ tsegsize = 2; // 2MB TSEG<br> mmiosize = 0x800; // 2GB MMIO<br>+ umasizem = gfxsize + gttsize + tsegsize;<br>+ /* Further reduce MTRR usage if it costs use less than<br>+ 16 MiB. */<br>+ if (ALIGN_UP(umasizem, 64) - umasizem <= 16)<br>+ umasizem = ALIGN_UP(umasizem, 64);<br>+ mmiostart = 0x1000 - mmiosize + umasizem;<br> tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB;<br>- tolud = MIN(0x1000 - mmiosize, tom);<br>+ tolud = MIN(mmiostart, tom);<br> <br> reclaim = false;<br> if ((tom - tolud) > 0x40)<br>@@ -1429,6 +1437,10 @@<br> pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud);<br> pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20);<br> pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20);<br>+ /* Set tseg size */<br>+ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);<br>+ reg8 &= ~(3 << 1);<br>+ pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8 | (1 << 1));<br> pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20);<br> }<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/21634">change 21634</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad </div>
<div style="display:none"> Gerrit-Change-Number: 21634 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>