[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Put S5-S0 AGESA heap into cbmem

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21594


Change subject: amd/stoneyridge: Put S5-S0 AGESA heap into cbmem
......................................................................

amd/stoneyridge: Put S5-S0 AGESA heap into cbmem

Now that soc/amd supports EARLY_CBMEM_INIT, put the HEAP into cbmem,
allowing better control of its cacheability in subsequent patches.
This relocates the heap initialization from the common directory into
stoneyridge (i.e. now expected to be non-generic), and places it later
than cbmem initialization.  The conversion relies on cbmem_add() first
searching cbmem for the ID before adding a new entry.

Change-Id: I9ff35eefb2a68879ff44c6e29f58635831b19848
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/common/agesawrapper.c
M src/soc/amd/common/heapmanager.c
M src/soc/amd/stoneyridge/romstage.c
3 files changed, 5 insertions(+), 8 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/21594/1

diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c
index 3ad4871..eea0ddc 100644
--- a/src/soc/amd/common/agesawrapper.c
+++ b/src/soc/amd/common/agesawrapper.c
@@ -174,8 +174,6 @@
 
 	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);
 	AmdReleaseStruct (&AmdParamStruct);
-	/* Initialize heap space */
-	EmptyHeap();
 
 	return status;
 }
diff --git a/src/soc/amd/common/heapmanager.c b/src/soc/amd/common/heapmanager.c
index 902fb15..58b072b 100644
--- a/src/soc/amd/common/heapmanager.c
+++ b/src/soc/amd/common/heapmanager.c
@@ -22,12 +22,7 @@
 
 void *GetHeapBase(AMD_CONFIG_PARAMS *StdHeader)
 {
-	void *heap = (void *)BIOS_HEAP_START_ADDRESS;
-
-	if (acpi_is_wakeup_s3())
-		heap = cbmem_find(CBMEM_ID_RESUME_SCRATCH);
-
-	return heap;
+	return cbmem_add(CBMEM_ID_RESUME_SCRATCH, BIOS_HEAP_SIZE);
 }
 
 void EmptyHeap(void)
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index da1d4b9..5ed02bb 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -24,6 +24,7 @@
 #include <soc/northbridge.h>
 #include <soc/southbridge.h>
 #include <amdblocks/psp.h>
+#include <BiosCallOuts.h>
 
 asmlinkage void car_stage_entry(void)
 {
@@ -70,6 +71,9 @@
 	post_code(0x43);
 	cbmem_initialize_empty();
 
+	/* Establish AGESA's heap. */
+	EmptyHeap();
+
 	/*
 	 * This writes contents to DRAM backing before teardown.
 	 * todo: move CAR teardown to postcar implementation and

-- 
To view, visit https://review.coreboot.org/21594
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9ff35eefb2a68879ff44c6e29f58635831b19848
Gerrit-Change-Number: 21594
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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