[coreboot-gerrit] Change in coreboot[master]: mb/gogle/poppy/*: Enable LTR for Root port 0

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/21548


Change subject: mb/gogle/poppy/*: Enable LTR for Root port 0
......................................................................

mb/gogle/poppy/*: Enable LTR for Root port 0

Enable LTR for Root port 0, where wifi card is connected.

BUG=b:65570878
TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported
     by AER driver for root port 0.

Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014
---
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
2 files changed, 4 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/21548/1

diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 0bd2efc..d4d7c2e 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -154,6 +154,8 @@
 	register "PcieRpClkReqNumber[0]" = "1"
 	# RP 1, Enable Advanced Error Reporting
 	register PcieRpAdvancedErrorReporting[0] = "1"
+	# RP 1, Enable Latency Tolerance Reporting Mechanism
+	register PcieRpLtrEnable[0] = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index ee9c5b7..cac618c 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -154,6 +154,8 @@
 	register "PcieRpClkReqNumber[0]" = "1"
 	# RP 1, Enable Advanced Error Reporting
 	register PcieRpAdvancedErrorReporting[0] = "1"
+	# RP 1, Enable Latency Tolerance Reporting Mechanism
+	register PcieRpLtrEnable[0] = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014
Gerrit-Change-Number: 21548
Gerrit-PatchSet: 1
Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi at intel.com>
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