<p>Rizwan Qureshi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21548">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/gogle/poppy/*: Enable LTR for Root port 0<br><br>Enable LTR for Root port 0, where wifi card is connected.<br><br>BUG=b:65570878<br>TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported<br>     by AER driver for root port 0.<br><br>Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014<br>---<br>M src/mainboard/google/poppy/variants/baseboard/devicetree.cb<br>M src/mainboard/google/poppy/variants/soraka/devicetree.cb<br>2 files changed, 4 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/21548/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb<br>index 0bd2efc..d4d7c2e 100644<br>--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb<br>+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb<br>@@ -154,6 +154,8 @@<br>  register "PcieRpClkReqNumber[0]" = "1"<br>    # RP 1, Enable Advanced Error Reporting<br>       register PcieRpAdvancedErrorReporting[0] = "1"<br>+     # RP 1, Enable Latency Tolerance Reporting Mechanism<br>+ register PcieRpLtrEnable[0] = "1"<br> <br>        register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"    # Type-C Port 1<br>       register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port<br>diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb<br>index ee9c5b7..cac618c 100644<br>--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb<br>+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb<br>@@ -154,6 +154,8 @@<br>   register "PcieRpClkReqNumber[0]" = "1"<br>    # RP 1, Enable Advanced Error Reporting<br>       register PcieRpAdvancedErrorReporting[0] = "1"<br>+     # RP 1, Enable Latency Tolerance Reporting Mechanism<br>+ register PcieRpLtrEnable[0] = "1"<br> <br>        register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"    # Type-C Port 1<br>       register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port<br></pre><p>To view, visit <a href="https://review.coreboot.org/21548">change 21548</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21548"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014 </div>
<div style="display:none"> Gerrit-Change-Number: 21548 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>