[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Store Memory Layout information into CAR

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21537


Change subject: soc/intel/skylake: Store Memory Layout information into CAR
......................................................................

soc/intel/skylake: Store Memory Layout information into CAR

This patch stores non-generic memory layout information
(i.e. PRMRR, TraceHub, PTT etc) into CAR for EBDA common code
usage.

Change-Id: I510d286ce5e0d8509ec31a65e971d5f19450364f
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/memmap.c
1 file changed, 42 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/21537/1

diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 6c64073..628421a 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/early_variables.h>
 #include <arch/io.h>
 #include <cbmem.h>
 #include <chip.h>
@@ -26,6 +27,31 @@
 #include <soc/smm.h>
 #include <soc/systemagent.h>
 #include <stdlib.h>
+
+struct soc_memory_info {
+	uint32_t cbmem_top;
+	uint32_t prmrr_size;
+	uint32_t tracehub_size;
+	uint32_t ptt_size;
+} __packed;
+
+static struct soc_memory_info memory_info CAR_GLOBAL;
+
+static struct soc_memory_info *get_memory_ptr(void)
+{
+	return car_get_var_ptr(&memory_info);
+}
+
+static void set_memory_info(uint32_t cbtop, uint32_t prmrr_size,
+		uint32_t tracehub_size, uint32_t ptt_size)
+{
+	struct soc_memory_info *mi = get_memory_ptr();
+
+	mi->cbmem_top = cbtop;
+	mi->prmrr_size = prmrr_size;
+	mi->tracehub_size = tracehub_size;
+	mi->ptt_size = ptt_size;
+}
 
 size_t mmap_region_granularity(void)
 {
@@ -139,7 +165,9 @@
 	const struct device *dev;
 	uint32_t dram_base;
 	uint32_t prmrr_base;
+	uint32_t tracehub_base;
 	size_t prmrr_size;
+	size_t tracehub_size = 0;
 
 	dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
 	if (!dev)
@@ -177,13 +205,18 @@
 			die("PRMRR Sizes that are > 1MB and < 32MB are not"
 					"supported!\n");
 
-		prmrr_base = dram_base - prmrr_size;
+		prmrr_base = dram_base;
+		dram_base -= prmrr_size;
 		if (prmrr_size >= 32*MiB)
-			prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB);
-		dram_base = prmrr_base;
+			dram_base = ALIGN_DOWN(dram_base, 128*MiB);
+
+		/* PRMRR Area Size */
+		prmrr_size = prmrr_base - dram_base;
 	}
 
 	if (config->ProbelessTrace) {
+		tracehub_base = dram_base;
+
 		/* GDXC MOT */
 		dram_base -= GDXC_MOT_MEMORY_SIZE;
 		/* Round down to natual boundary accroding to PSMI size */
@@ -192,11 +225,17 @@
 		dram_base -= GDXC_IOT_MEMORY_SIZE;
 		/* PSMI buffer area */
 		dram_base -= PSMI_BUFFER_AREA_SIZE;
+
+		/* TraceHub Area Size */
+		tracehub_size = tracehub_base - dram_base;
 	}
 
 	if (is_ptt_enable())
 		dram_base -= 4*KiB; /* Allocate 4KB for PTT if enable */
 
+	set_memory_info(dram_base, prmrr_size, tracehub_size,
+			is_ptt_enable() ? 4*KiB : 0);
+
 	return dram_base;
 }
 

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I510d286ce5e0d8509ec31a65e971d5f19450364f
Gerrit-Change-Number: 21537
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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