<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21537">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Store Memory Layout information into CAR<br><br>This patch stores non-generic memory layout information<br>(i.e. PRMRR, TraceHub, PTT etc) into CAR for EBDA common code<br>usage.<br><br>Change-Id: I510d286ce5e0d8509ec31a65e971d5f19450364f<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/skylake/memmap.c<br>1 file changed, 42 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/21537/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c<br>index 6c64073..628421a 100644<br>--- a/src/soc/intel/skylake/memmap.c<br>+++ b/src/soc/intel/skylake/memmap.c<br>@@ -14,6 +14,7 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>+#include <arch/early_variables.h><br> #include <arch/io.h><br> #include <cbmem.h><br> #include <chip.h><br>@@ -26,6 +27,31 @@<br> #include <soc/smm.h><br> #include <soc/systemagent.h><br> #include <stdlib.h><br>+<br>+struct soc_memory_info {<br>+   uint32_t cbmem_top;<br>+  uint32_t prmrr_size;<br>+ uint32_t tracehub_size;<br>+      uint32_t ptt_size;<br>+} __packed;<br>+<br>+static struct soc_memory_info memory_info CAR_GLOBAL;<br>+<br>+static struct soc_memory_info *get_memory_ptr(void)<br>+{<br>+     return car_get_var_ptr(&memory_info);<br>+}<br>+<br>+static void set_memory_info(uint32_t cbtop, uint32_t prmrr_size,<br>+          uint32_t tracehub_size, uint32_t ptt_size)<br>+{<br>+       struct soc_memory_info *mi = get_memory_ptr();<br>+<br>+    mi->cbmem_top = cbtop;<br>+    mi->prmrr_size = prmrr_size;<br>+      mi->tracehub_size = tracehub_size;<br>+        mi->ptt_size = ptt_size;<br>+}<br> <br> size_t mmap_region_granularity(void)<br> {<br>@@ -139,7 +165,9 @@<br>    const struct device *dev;<br>     uint32_t dram_base;<br>   uint32_t prmrr_base;<br>+ uint32_t tracehub_base;<br>       size_t prmrr_size;<br>+   size_t tracehub_size = 0;<br> <br>  dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));<br>        if (!dev)<br>@@ -177,13 +205,18 @@<br>                      die("PRMRR Sizes that are > 1MB and < 32MB are not"<br>                                   "supported!\n");<br> <br>-                prmrr_base = dram_base - prmrr_size;<br>+         prmrr_base = dram_base;<br>+              dram_base -= prmrr_size;<br>              if (prmrr_size >= 32*MiB)<br>-                 prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB);<br>-                dram_base = prmrr_base;<br>+                      dram_base = ALIGN_DOWN(dram_base, 128*MiB);<br>+<br>+               /* PRMRR Area Size */<br>+                prmrr_size = prmrr_base - dram_base;<br>  }<br> <br>  if (config->ProbelessTrace) {<br>+             tracehub_base = dram_base;<br>+<br>                 /* GDXC MOT */<br>                dram_base -= GDXC_MOT_MEMORY_SIZE;<br>            /* Round down to natual boundary accroding to PSMI size */<br>@@ -192,11 +225,17 @@<br>             dram_base -= GDXC_IOT_MEMORY_SIZE;<br>            /* PSMI buffer area */<br>                dram_base -= PSMI_BUFFER_AREA_SIZE;<br>+<br>+               /* TraceHub Area Size */<br>+             tracehub_size = tracehub_base - dram_base;<br>    }<br> <br>  if (is_ptt_enable())<br>          dram_base -= 4*KiB; /* Allocate 4KB for PTT if enable */<br> <br>+  set_memory_info(dram_base, prmrr_size, tracehub_size,<br>+                        is_ptt_enable() ? 4*KiB : 0);<br>+<br>      return dram_base;<br> }<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/21537">change 21537</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21537"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I510d286ce5e0d8509ec31a65e971d5f19450364f </div>
<div style="display:none"> Gerrit-Change-Number: 21537 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>