[coreboot-gerrit] Change in coreboot[master]: [UNTESTED, NOTFORMERGE]mb/gigabyte/m57sli-s4: Implement s3 resume

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21460


Change subject: [UNTESTED,NOTFORMERGE]mb/gigabyte/m57sli-s4: Implement s3 resume
......................................................................

[UNTESTED,NOTFORMERGE]mb/gigabyte/m57sli-s4: Implement s3 resume

Change-Id: I088029c78c3f09edf1a81483db5f269ae7ab9604
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/gigabyte/m57sli/Kconfig
M src/mainboard/gigabyte/m57sli/dsdt.asl
M src/northbridge/amd/amdk8/raminit_f_dqs.c
M src/southbridge/nvidia/mcp55/early_setup_car.c
M src/southbridge/nvidia/mcp55/mcp55.h
5 files changed, 41 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/21460/1

diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig
index 2847377..94c1412 100644
--- a/src/mainboard/gigabyte/m57sli/Kconfig
+++ b/src/mainboard/gigabyte/m57sli/Kconfig
@@ -22,6 +22,7 @@
 	select QRANK_DIMM_SUPPORT
 	select K8_ALLOCATE_IO_RANGE
 	select SET_FIDVID
+	select HAVE_ACPI_RESUME
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/gigabyte/m57sli/dsdt.asl b/src/mainboard/gigabyte/m57sli/dsdt.asl
index c53f36a..101d9da 100644
--- a/src/mainboard/gigabyte/m57sli/dsdt.asl
+++ b/src/mainboard/gigabyte/m57sli/dsdt.asl
@@ -25,9 +25,11 @@
 
 	/* For now only define 2 power states:
 	 *  - S0 which is fully on
+	 *  - S3
 	 *  - S5 which is soft off
 	 */
 	Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+	Name (\_S3, Package () { 0x05, 0x00, 0x00, 0x00 })
 	Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
 
 	/* Root of the bus hierarchy */
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 64b0c64..8cda2d6 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -20,8 +20,10 @@
 #include <arch/early_variables.h>
 #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700)
 #include <southbridge/amd/sb700/sb700.h>
-#else /* IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_K8T890) */
+#elseif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_K8T890)
 #include <southbridge/via/k8t890/k8t890.h>
+#else /* IS_ENABLED(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55) */
+#include <southbridge/nvidia/mcp55/mcp55.h>
 #endif
 
 //0: mean no debug info
diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c
index 8019a8e..10ac99c 100644
--- a/src/southbridge/nvidia/mcp55/early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c
@@ -15,6 +15,8 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/acpi.h>
+
 #ifdef UNUSED_CODE
 int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val);
 
@@ -390,3 +392,34 @@
 
 	return 0;
 }
+
+
+int acpi_get_sleep_type(void)
+{
+	u16 tmp;
+	tmp = inw(ACPICTRL_IO_BASE + 0x04);
+	return ((tmp & (7 << 10) >> 10));
+}
+
+int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
+{
+	int i;
+	printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
+	for (i = 0; i < size; i++)
+		cmos_write((dword >> (8 * i)) & 0xff, 128 + nvram_pos++);
+	return nvram_pos;
+}
+
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+{
+	int i;
+
+	*old_dword = 0;
+
+	for (i = 0; i < size; i++)
+		*old_dword |= cmos_read(128 + nvram_pos++) << (i * 8);
+
+	printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n",
+		*old_dword, size, nvram_pos-size);
+	return nvram_pos;
+}
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index a244b82..a87acf8 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -40,6 +40,8 @@
 int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address);
 int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address,
 		unsigned char val);
+int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 #endif
 
 #endif

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I088029c78c3f09edf1a81483db5f269ae7ab9604
Gerrit-Change-Number: 21460
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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