<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21460">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[UNTESTED,NOTFORMERGE]mb/gigabyte/m57sli-s4: Implement s3 resume<br><br>Change-Id: I088029c78c3f09edf1a81483db5f269ae7ab9604<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/gigabyte/m57sli/Kconfig<br>M src/mainboard/gigabyte/m57sli/dsdt.asl<br>M src/northbridge/amd/amdk8/raminit_f_dqs.c<br>M src/southbridge/nvidia/mcp55/early_setup_car.c<br>M src/southbridge/nvidia/mcp55/mcp55.h<br>5 files changed, 41 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/21460/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig<br>index 2847377..94c1412 100644<br>--- a/src/mainboard/gigabyte/m57sli/Kconfig<br>+++ b/src/mainboard/gigabyte/m57sli/Kconfig<br>@@ -22,6 +22,7 @@<br>      select QRANK_DIMM_SUPPORT<br>     select K8_ALLOCATE_IO_RANGE<br>   select SET_FIDVID<br>+    select HAVE_ACPI_RESUME<br> <br> config MAINBOARD_DIR<br>     string<br>diff --git a/src/mainboard/gigabyte/m57sli/dsdt.asl b/src/mainboard/gigabyte/m57sli/dsdt.asl<br>index c53f36a..101d9da 100644<br>--- a/src/mainboard/gigabyte/m57sli/dsdt.asl<br>+++ b/src/mainboard/gigabyte/m57sli/dsdt.asl<br>@@ -25,9 +25,11 @@<br> <br>        /* For now only define 2 power states:<br>         *  - S0 which is fully on<br>+    *  - S3<br>       *  - S5 which is soft off<br>     */<br>   Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })<br>+   Name (\_S3, Package () { 0x05, 0x00, 0x00, 0x00 })<br>    Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })<br> <br>         /* Root of the bus hierarchy */<br>diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c<br>index 64b0c64..8cda2d6 100644<br>--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c<br>+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c<br>@@ -20,8 +20,10 @@<br> #include <arch/early_variables.h><br> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700)<br> #include <southbridge/amd/sb700/sb700.h><br>-#else /* IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_K8T890) */<br>+#elseif IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_K8T890)<br> #include <southbridge/via/k8t890/k8t890.h><br>+#else /* IS_ENABLED(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55) */<br>+#include <southbridge/nvidia/mcp55/mcp55.h><br> #endif<br> <br> //0: mean no debug info<br>diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c<br>index 8019a8e..10ac99c 100644<br>--- a/src/southbridge/nvidia/mcp55/early_setup_car.c<br>+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c<br>@@ -15,6 +15,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>+#include <arch/acpi.h><br>+<br> #ifdef UNUSED_CODE<br> int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val);<br> <br>@@ -390,3 +392,34 @@<br> <br>  return 0;<br> }<br>+<br>+<br>+int acpi_get_sleep_type(void)<br>+{<br>+      u16 tmp;<br>+     tmp = inw(ACPICTRL_IO_BASE + 0x04);<br>+  return ((tmp & (7 << 10) >> 10));<br>+}<br>+<br>+int s3_save_nvram_early(u32 dword, int size, int nvram_pos)<br>+{<br>+   int i;<br>+       printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);<br>+    for (i = 0; i < size; i++)<br>+                cmos_write((dword >> (8 * i)) & 0xff, 128 + nvram_pos++);<br>+  return nvram_pos;<br>+}<br>+<br>+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)<br>+{<br>+      int i;<br>+<br>+    *old_dword = 0;<br>+<br>+   for (i = 0; i < size; i++)<br>+                *old_dword |= cmos_read(128 + nvram_pos++) << (i * 8);<br>+<br>+      printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n",<br>+              *old_dword, size, nvram_pos-size);<br>+   return nvram_pos;<br>+}<br>diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h<br>index a244b82..a87acf8 100644<br>--- a/src/southbridge/nvidia/mcp55/mcp55.h<br>+++ b/src/southbridge/nvidia/mcp55/mcp55.h<br>@@ -40,6 +40,8 @@<br> int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address);<br> int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address,<br>               unsigned char val);<br>+int s3_save_nvram_early(u32 dword, int size, int nvram_pos);<br>+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);<br> #endif<br> <br> #endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/21460">change 21460</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop=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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I088029c78c3f09edf1a81483db5f269ae7ab9604 </div>
<div style="display:none"> Gerrit-Change-Number: 21460 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>