[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Update common rtc code

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21433


Change subject: soc/intel/common/block: Update common rtc code
......................................................................

soc/intel/common/block: Update common rtc code

Move rtc init code into common area and update the implementation for
apollolake to avoid build break.

Change-Id: I702ce0efba25cb6fde33cc15698ae44312742367
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/apollolake/lpc.c
M src/soc/intel/common/block/include/intelblocks/rtc.h
M src/soc/intel/common/block/rtc/Makefile.inc
M src/soc/intel/common/block/rtc/rtc.c
4 files changed, 32 insertions(+), 11 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/21433/8

diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index 6c7ffff..0cd58de 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -83,23 +83,16 @@
 	gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios));
 }
 
-static void rtc_init(void)
+int soc_get_rtc_failed(void)
 {
-	int rtc_fail;
 	const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
 
 	if (!ps) {
 		printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n");
-		return;
+		return 1;
 	}
 
-	rtc_fail = !!(ps->gen_pmcon1 & RPS);
-	/* Ensure the date is set including century byte. */
-	cmos_check_update_date();
-	if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS))
-		init_vbnv_cmos(rtc_fail);
-	else
-		cmos_init(rtc_fail);
+	return !!(ps->gen_pmcon1 & RPS);
 }
 
 void lpc_init(struct device *dev)
diff --git a/src/soc/intel/common/block/include/intelblocks/rtc.h b/src/soc/intel/common/block/include/intelblocks/rtc.h
index 1556026..c6507c8 100644
--- a/src/soc/intel/common/block/include/intelblocks/rtc.h
+++ b/src/soc/intel/common/block/include/intelblocks/rtc.h
@@ -18,4 +18,9 @@
 
 void enable_rtc_upper_bank(void);
 
+/* Expect return rtc failed bootlean in case of coin removal */
+int soc_get_rtc_failed(void);
+
+void rtc_init(void);
+
 #endif	/* SOC_INTEL_COMMON_BLOCK_RTC_H */
diff --git a/src/soc/intel/common/block/rtc/Makefile.inc b/src/soc/intel/common/block/rtc/Makefile.inc
index 2d2d4e3..95f6659 100644
--- a/src/soc/intel/common/block/rtc/Makefile.inc
+++ b/src/soc/intel/common/block/rtc/Makefile.inc
@@ -1 +1,3 @@
 bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_RTC) += rtc.c
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_RTC) += rtc.c
diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c
index ea99870..04c0768 100644
--- a/src/soc/intel/common/block/rtc/rtc.c
+++ b/src/soc/intel/common/block/rtc/rtc.c
@@ -13,9 +13,11 @@
  * GNU General Public License for more details.
  */
 
-#include <soc/pcr_ids.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/rtc.h>
+#include <soc/pcr_ids.h>
+#include <pc80/mc146818rtc.h>
+#include <vboot/vbnv.h>
 
 /* RTC PCR configuration */
 #define PCR_RTC_CONF		0x3400
@@ -29,3 +31,22 @@
 	/* Enable upper 128 bytes of CMOS */
 	pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN);
 }
+
+__attribute__((weak)) int soc_get_rtc_failed(void)
+{
+	return 0;
+}
+
+void rtc_init(void)
+{
+	int rtc_failed;
+
+	rtc_failed = soc_get_rtc_failed();
+	/* Ensure the date is set including century byte. */
+	cmos_check_update_date();
+
+	if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS))
+		init_vbnv_cmos(rtc_failed);
+	else
+		cmos_init(rtc_failed);
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I702ce0efba25cb6fde33cc15698ae44312742367
Gerrit-Change-Number: 21433
Gerrit-PatchSet: 8
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Andrex Andraos <andrex.andraos at intel.corp-partner.google.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: John Zhao <john.zhao at intel.com>
Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula at intel.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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