[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake:Fix SPI WP disable status check

[Ravishankar Sarawadi (Code Review)]

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/21449


Change subject: soc/intel/skylake:Fix SPI WP disable status check
......................................................................

soc/intel/skylake:Fix SPI WP disable status check

Use FST SPI write protect disable bit from BIOS_CONTROL register
to check write protect status.

Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/include/intelblocks/fast_spi.h
M src/soc/intel/skylake/smihandler.c
3 files changed, 28 insertions(+), 7 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/21449/1

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 078e0ae..87cafb9 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -274,3 +274,21 @@
 	/* Initialize SPI to allow BIOS to write/erase on flash. */
 	fast_spi_init();
 }
+
+/* Read SPI Write Protect disable status. */
+bool fast_spi_wpd_status(void)
+{
+	return pci_read_config16(PCH_DEV_SPI, SPIBAR_BIOS_CONTROL) &
+		SPIBAR_BIOS_CONTROL_WPD;
+}
+
+/* Enable SPI Write Protect. */
+void fast_spi_enable_wp(void)
+{
+	device_t dev = PCH_DEV_SPI;
+	uint8_t bios_cntl;
+
+	bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
+	bios_cntl &= ~SPIBAR_BIOS_CONTROL_WPD;
+	pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl);
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
index 086143b..6499ca5 100644
--- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h
+++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
@@ -74,11 +74,18 @@
  * Caching.
  */
 void fast_spi_early_init(uintptr_t spi_base_address);
-
 /*
  * Fast SPI flash controller structure to allow SoCs to define bus-controller
  * mapping.
  */
 extern const struct spi_ctrlr fast_spi_flash_ctrlr;
+/*
+ * Read SPI Write protect disable bit.
+ */
+bool fast_spi_wpd_status(void);
+/*
+ * Enable SPI Write protect.
+ */
+void fast_spi_enable_wp(void);
 
 #endif	/* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index 3e79065..7409ed7 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -31,7 +31,6 @@
 #include <pc80/mc146818rtc.h>
 #include <spi-generic.h>
 #include <soc/iomap.h>
-#include <soc/lpc.h>
 #include <soc/nvs.h>
 #include <soc/pci_devs.h>
 #include <soc/pch.h>
@@ -403,9 +402,7 @@
 		return;
 
 	if (tco_sts & (1 << 8)) { /* BIOSWR */
-		u8 bios_cntl = pci_read_config16(PCH_DEV_SPI, BIOS_CNTL);
-
-		if (bios_cntl & 1) {
+		if (fast_spi_wpd_status()) {
 			/*
 			 * BWE is RW, so the SMI was caused by a
 			 * write to BWE, not by a write to the BIOS
@@ -417,8 +414,7 @@
 			 * box.
 			 */
 			printk(BIOS_DEBUG, "Switching back to RO\n");
-			pci_write_config32(PCH_DEV_SPI, BIOS_CNTL,
-					   (bios_cntl & ~1));
+			fast_spi_enable_wp();
 		} /* No else for now? */
 	} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
 		/* Handle TCO timeout */

-- 
To view, visit https://review.coreboot.org/21449
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a
Gerrit-Change-Number: 21449
Gerrit-PatchSet: 1
Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20170907/c71fe75e/attachment.html>