<p>Ravishankar Sarawadi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21449">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake:Fix SPI WP disable status check<br><br>Use FST SPI write protect disable bit from BIOS_CONTROL register<br>to check write protect status.<br><br>Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a<br>Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com><br>---<br>M src/soc/intel/common/block/fast_spi/fast_spi.c<br>M src/soc/intel/common/block/include/intelblocks/fast_spi.h<br>M src/soc/intel/skylake/smihandler.c<br>3 files changed, 28 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/21449/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c<br>index 078e0ae..87cafb9 100644<br>--- a/src/soc/intel/common/block/fast_spi/fast_spi.c<br>+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c<br>@@ -274,3 +274,21 @@<br>      /* Initialize SPI to allow BIOS to write/erase on flash. */<br>   fast_spi_init();<br> }<br>+<br>+/* Read SPI Write Protect disable status. */<br>+bool fast_spi_wpd_status(void)<br>+{<br>+  return pci_read_config16(PCH_DEV_SPI, SPIBAR_BIOS_CONTROL) &<br>+             SPIBAR_BIOS_CONTROL_WPD;<br>+}<br>+<br>+/* Enable SPI Write Protect. */<br>+void fast_spi_enable_wp(void)<br>+{<br>+        device_t dev = PCH_DEV_SPI;<br>+  uint8_t bios_cntl;<br>+<br>+        bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);<br>+      bios_cntl &= ~SPIBAR_BIOS_CONTROL_WPD;<br>+   pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl);<br>+}<br>diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h<br>index 086143b..6499ca5 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h<br>@@ -74,11 +74,18 @@<br>  * Caching.<br>  */<br> void fast_spi_early_init(uintptr_t spi_base_address);<br>-<br> /*<br>  * Fast SPI flash controller structure to allow SoCs to define bus-controller<br>  * mapping.<br>  */<br> extern const struct spi_ctrlr fast_spi_flash_ctrlr;<br>+/*<br>+ * Read SPI Write protect disable bit.<br>+ */<br>+bool fast_spi_wpd_status(void);<br>+/*<br>+ * Enable SPI Write protect.<br>+ */<br>+void fast_spi_enable_wp(void);<br> <br> #endif        /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */<br>diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c<br>index 3e79065..7409ed7 100644<br>--- a/src/soc/intel/skylake/smihandler.c<br>+++ b/src/soc/intel/skylake/smihandler.c<br>@@ -31,7 +31,6 @@<br> #include <pc80/mc146818rtc.h><br> #include <spi-generic.h><br> #include <soc/iomap.h><br>-#include <soc/lpc.h><br> #include <soc/nvs.h><br> #include <soc/pci_devs.h><br> #include <soc/pch.h><br>@@ -403,9 +402,7 @@<br>               return;<br> <br>    if (tco_sts & (1 << 8)) { /* BIOSWR */<br>-             u8 bios_cntl = pci_read_config16(PCH_DEV_SPI, BIOS_CNTL);<br>-<br>-         if (bios_cntl & 1) {<br>+             if (fast_spi_wpd_status()) {<br>                  /*<br>                     * BWE is RW, so the SMI was caused by a<br>                       * write to BWE, not by a write to the BIOS<br>@@ -417,8 +414,7 @@<br>                       * box.<br>                        */<br>                   printk(BIOS_DEBUG, "Switching back to RO\n");<br>-                      pci_write_config32(PCH_DEV_SPI, BIOS_CNTL,<br>-                                      (bios_cntl & ~1));<br>+                    fast_spi_enable_wp();<br>                 } /* No else for now? */<br>      } else if (tco_sts & (1 << 3)) { /* TIMEOUT */<br>              /* Handle TCO timeout */<br></pre><p>To view, visit <a href="https://review.coreboot.org/21449">change 21449</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21449"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a </div>
<div style="display:none"> Gerrit-Change-Number: 21449 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>