[coreboot-gerrit] Change in coreboot[master]: mainboard/intel/d525mw: SuperIO is W83627DHG

[Philipp Ammann (Code Review)]

Philipp Ammann has uploaded this change for review. ( https://review.coreboot.org/21422


Change subject: mainboard/intel/d525mw: SuperIO is W83627DHG
......................................................................

mainboard/intel/d525mw: SuperIO is W83627DHG

Replace W83627THG includes from the D510MO with D83627DHG.

Change-Id: I6c80878966193011ac30dfb8d4fadf3318285058
Signed-off-by: Philipp Ammann <trilean at users.noreply.github.com>
---
M src/mainboard/intel/d525mw/Kconfig
M src/mainboard/intel/d525mw/devicetree.cb
M src/mainboard/intel/d525mw/romstage.c
3 files changed, 4 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/21422/1

diff --git a/src/mainboard/intel/d525mw/Kconfig b/src/mainboard/intel/d525mw/Kconfig
index 4f3c998..b73fa5f 100644
--- a/src/mainboard/intel/d525mw/Kconfig
+++ b/src/mainboard/intel/d525mw/Kconfig
@@ -20,7 +20,7 @@
 	select CPU_INTEL_SOCKET_FCBGA559
 	select NORTHBRIDGE_INTEL_PINEVIEW
 	select SOUTHBRIDGE_INTEL_I82801GX
-	select SUPERIO_WINBOND_W83627THG
+	select SUPERIO_WINBOND_W83627DHG
 	select HAVE_ACPI_TABLES
 	select HAVE_ACPI_RESUME
 	select BOARD_ROMSIZE_KB_1024
diff --git a/src/mainboard/intel/d525mw/devicetree.cb b/src/mainboard/intel/d525mw/devicetree.cb
index c5b885f..29343e0 100644
--- a/src/mainboard/intel/d525mw/devicetree.cb
+++ b/src/mainboard/intel/d525mw/devicetree.cb
@@ -56,7 +56,7 @@
       device pci 1d.7 on end		# USB
       device pci 1e.0 on end		# PCI bridge
       device pci 1f.0 on		# ISA bridge
-        chip superio/winbond/w83627thg	# Super I/O
+        chip superio/winbond/w83627dhg	# Super I/O
           device pnp 4e.0 off end	# Floppy
           device pnp 4e.1 on		# Parallel port
             io 0x60 = 0x378
diff --git a/src/mainboard/intel/d525mw/romstage.c b/src/mainboard/intel/d525mw/romstage.c
index 44f203f..3ef23c5 100644
--- a/src/mainboard/intel/d525mw/romstage.c
+++ b/src/mainboard/intel/d525mw/romstage.c
@@ -27,7 +27,7 @@
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/lapic.h>
-#include <superio/winbond/w83627thg/w83627thg.h>
+#include <superio/winbond/w83627dhg/w83627dhg.h>
 #include <superio/winbond/common/winbond.h>
 #include <lib.h>
 #include <arch/stages.h>
@@ -35,7 +35,7 @@
 #include <romstage_handoff.h>
 #include <timestamp.h>
 
-#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
+#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1)
 #define SUPERIO_DEV PNP_DEV(0x4e, 0)
 
 

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6c80878966193011ac30dfb8d4fadf3318285058
Gerrit-Change-Number: 21422
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Ammann
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