[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Make SCI selectable

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/21417


Change subject: soc/intel/apollolake: Make SCI selectable
......................................................................

soc/intel/apollolake: Make SCI selectable

The System Control Interrupt is route per default to IRQ 9. Some
mainboards use IRQ 9 for different purpose. Therefore it is necessary to
make the SCI selectable on Apollo Lake.

Change-Id: Ice665ae3d8b74d344ffcb33b6ef6ff9631b2b093
Signed-off-by: Mario Scheithauer <mario.scheithauer at siemens.com>
---
M src/soc/intel/apollolake/acpi.c
M src/soc/intel/apollolake/include/soc/pm.h
2 files changed, 45 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/21417/1

diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 1826b48..2386051 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -17,11 +17,13 @@
 
 #include <arch/acpi.h>
 #include <arch/acpigen.h>
+#include <arch/io.h>
 #include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
 #include <cbmem.h>
 #include <cpu/x86/smm.h>
 #include <cpu/cpu.h>
+#include <intelblocks/pmclib.h>
 #include <soc/acpi.h>
 #include <soc/intel/common/acpi.h>
 #include <soc/iomap.h>
@@ -52,7 +54,39 @@
 
 static int acpi_sci_irq(void)
 {
-	int sci_irq = 9;
+	static int8_t sci_irq = 0;
+	uint32_t irq_sel_2 = 0;
+	uintptr_t pmc_bar = 0;
+
+	/* If this function was already called, just return the stored value. */
+	if (sci_irq)
+		return sci_irq;
+
+	/* Read PMC base address from soc. */
+	pmc_bar = soc_read_pmc_base();
+	irq_sel_2 = read32((void *)pmc_bar + IRQ_SEL_2) & SCI_IRQ_MASK;
+
+	switch (irq_sel_2) {
+	case SCI_IRQ_9:
+		sci_irq = (irq_sel_2 >> 24) & 0xF;
+		break;
+	case SCI_IRQ_10:
+	case SCI_IRQ_11:
+		sci_irq = ((irq_sel_2 >> 24) & 0xF) + 9;
+		break;
+	case SCI_IRQ_20:
+	case SCI_IRQ_21:
+	case SCI_IRQ_22:
+	case SCI_IRQ_23:
+		sci_irq = ((irq_sel_2 >> 24) & 0xF) + 16;
+		break;
+	default:
+		printk(BIOS_ERR, "Invalid SCI route! Defaulting to IRQ9.\n");
+		sci_irq = 9;
+		break;
+	}
+
+	printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
 	return sci_irq;
 }
 
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 3be3955..5c066df 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -180,6 +180,16 @@
 #define GPIO_GPE_CFG		0x1050
 #define  GPE0_DWX_MASK		0xf
 #define GPE0_DW_SHIFT(x)	(4 + 4*(x))
+#define IRQ_SEL_2              0x106C
+#define  SCI_IRQ_MASK          0x0F000000
+#define  SCI_IRQ_9             (9 << 24)
+#define  SCI_IRQ_10            (1 << 24)
+#define  SCI_IRQ_11            (2 << 24)
+#define  SCI_IRQ_DIS           (3 << 24)
+#define  SCI_IRQ_20            (4 << 24)
+#define  SCI_IRQ_21            (5 << 24)
+#define  SCI_IRQ_22            (6 << 24)
+#define  SCI_IRQ_23            (7 << 24)
 
 #if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
 #define PMC_GPE_N_95_64		8

-- 
To view, visit https://review.coreboot.org/21417
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ice665ae3d8b74d344ffcb33b6ef6ff9631b2b093
Gerrit-Change-Number: 21417
Gerrit-PatchSet: 1
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20170906/eaeaa8be/attachment-0001.html>