<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21417">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Make SCI selectable<br><br>The System Control Interrupt is route per default to IRQ 9. Some<br>mainboards use IRQ 9 for different purpose. Therefore it is necessary to<br>make the SCI selectable on Apollo Lake.<br><br>Change-Id: Ice665ae3d8b74d344ffcb33b6ef6ff9631b2b093<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/soc/intel/apollolake/acpi.c<br>M src/soc/intel/apollolake/include/soc/pm.h<br>2 files changed, 45 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/21417/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c<br>index 1826b48..2386051 100644<br>--- a/src/soc/intel/apollolake/acpi.c<br>+++ b/src/soc/intel/apollolake/acpi.c<br>@@ -17,11 +17,13 @@<br> <br> #include <arch/acpi.h><br> #include <arch/acpigen.h><br>+#include <arch/io.h><br> #include <arch/ioapic.h><br> #include <arch/smp/mpspec.h><br> #include <cbmem.h><br> #include <cpu/x86/smm.h><br> #include <cpu/cpu.h><br>+#include <intelblocks/pmclib.h><br> #include <soc/acpi.h><br> #include <soc/intel/common/acpi.h><br> #include <soc/iomap.h><br>@@ -52,7 +54,39 @@<br> <br> static int acpi_sci_irq(void)<br> {<br>-  int sci_irq = 9;<br>+     static int8_t sci_irq = 0;<br>+   uint32_t irq_sel_2 = 0;<br>+      uintptr_t pmc_bar = 0;<br>+<br>+    /* If this function was already called, just return the stored value. */<br>+     if (sci_irq)<br>+         return sci_irq;<br>+<br>+   /* Read PMC base address from soc. */<br>+        pmc_bar = soc_read_pmc_base();<br>+       irq_sel_2 = read32((void *)pmc_bar + IRQ_SEL_2) & SCI_IRQ_MASK;<br>+<br>+       switch (irq_sel_2) {<br>+ case SCI_IRQ_9:<br>+              sci_irq = (irq_sel_2 >> 24) & 0xF;<br>+         break;<br>+       case SCI_IRQ_10:<br>+     case SCI_IRQ_11:<br>+             sci_irq = ((irq_sel_2 >> 24) & 0xF) + 9;<br>+           break;<br>+       case SCI_IRQ_20:<br>+     case SCI_IRQ_21:<br>+     case SCI_IRQ_22:<br>+     case SCI_IRQ_23:<br>+             sci_irq = ((irq_sel_2 >> 24) & 0xF) + 16;<br>+          break;<br>+       default:<br>+             printk(BIOS_ERR, "Invalid SCI route! Defaulting to IRQ9.\n");<br>+              sci_irq = 9;<br>+         break;<br>+       }<br>+<br>+ printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);<br>      return sci_irq;<br> }<br> <br>diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h<br>index 3be3955..5c066df 100644<br>--- a/src/soc/intel/apollolake/include/soc/pm.h<br>+++ b/src/soc/intel/apollolake/include/soc/pm.h<br>@@ -180,6 +180,16 @@<br> #define GPIO_GPE_CFG                0x1050<br> #define  GPE0_DWX_MASK         0xf<br> #define GPE0_DW_SHIFT(x)  (4 + 4*(x))<br>+#define IRQ_SEL_2              0x106C<br>+#define  SCI_IRQ_MASK          0x0F000000<br>+#define  SCI_IRQ_9             (9 << 24)<br>+#define  SCI_IRQ_10            (1 << 24)<br>+#define  SCI_IRQ_11            (2 << 24)<br>+#define  SCI_IRQ_DIS           (3 << 24)<br>+#define  SCI_IRQ_20            (4 << 24)<br>+#define  SCI_IRQ_21            (5 << 24)<br>+#define  SCI_IRQ_22            (6 << 24)<br>+#define  SCI_IRQ_23            (7 << 24)<br> <br> #if IS_ENABLED(CONFIG_SOC_INTEL_GLK)<br> #define PMC_GPE_N_95_64             8<br></pre><p>To view, visit <a href="https://review.coreboot.org/21417">change 21417</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21417"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ice665ae3d8b74d344ffcb33b6ef6ff9631b2b093 </div>
<div style="display:none"> Gerrit-Change-Number: 21417 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>