[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: Add SoC stepping identify helper
Matt DeVillier (Code Review)
gerrit at coreboot.org
Mon Sep 4 04:04:35 CEST 2017
Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21371
Change subject: soc/intel/braswell: Add SoC stepping identify helper
......................................................................
soc/intel/braswell: Add SoC stepping identify helper
Adapted from Chromium commit 9756af8.
Add SOC helper to identify BSW SoC stepping. Will be used to
override USB2 phy setting based on stepping in subsequent commit.
Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng at quantatw.com>
Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/braswell/chip.c
M src/soc/intel/braswell/include/soc/ramstage.h
2 files changed, 152 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/21371/1
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 91cb384..e0c1a51 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -169,6 +169,7 @@
params->I2C4Frequency = config->I2C4Frequency;
params->I2C5Frequency = config->I2C5Frequency;
params->I2C6Frequency = config->I2C6Frequency;
+
}
void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
@@ -363,3 +364,83 @@
struct pci_operations soc_pci_ops = {
.set_subsystem = &pci_set_subsystem,
};
+
+/**
+ Return SoC stepping type
+
+ @retval SOC_STEPPING SoC stepping type
+**/
+int SocStepping(void)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+ u8 revid = pci_read_config8(dev, 0x8);
+
+ switch (revid & B_PCH_LPC_RID_STEPPING_MASK) {
+ case V_PCH_LPC_RID_A0:
+ return SocA0;
+ case V_PCH_LPC_RID_A1:
+ return SocA1;
+ case V_PCH_LPC_RID_A2:
+ return SocA2;
+ case V_PCH_LPC_RID_A3:
+ return SocA3;
+ case V_PCH_LPC_RID_A4:
+ return SocA4;
+ case V_PCH_LPC_RID_A5:
+ return SocA5;
+ case V_PCH_LPC_RID_A6:
+ return SocA6;
+ case V_PCH_LPC_RID_A7:
+ return SocA7;
+ case V_PCH_LPC_RID_B0:
+ return SocB0;
+ case V_PCH_LPC_RID_B1:
+ return SocB1;
+ case V_PCH_LPC_RID_B2:
+ return SocB2;
+ case V_PCH_LPC_RID_B3:
+ return SocB3;
+ case V_PCH_LPC_RID_B4:
+ return SocB4;
+ case V_PCH_LPC_RID_B5:
+ return SocB5;
+ case V_PCH_LPC_RID_B6:
+ return SocB6;
+ case V_PCH_LPC_RID_B7:
+ return SocB7;
+ case V_PCH_LPC_RID_C0:
+ return SocC0;
+ case V_PCH_LPC_RID_C1:
+ return SocC1;
+ case V_PCH_LPC_RID_C2:
+ return SocC2;
+ case V_PCH_LPC_RID_C3:
+ return SocC3;
+ case V_PCH_LPC_RID_C4:
+ return SocC4;
+ case V_PCH_LPC_RID_C5:
+ return SocC5;
+ case V_PCH_LPC_RID_C6:
+ return SocC6;
+ case V_PCH_LPC_RID_C7:
+ return SocC7;
+ case V_PCH_LPC_RID_D0:
+ return SocD0;
+ case V_PCH_LPC_RID_D1:
+ return SocD1;
+ case V_PCH_LPC_RID_D2:
+ return SocD2;
+ case V_PCH_LPC_RID_D3:
+ return SocD3;
+ case V_PCH_LPC_RID_D4:
+ return SocD4;
+ case V_PCH_LPC_RID_D5:
+ return SocD5;
+ case V_PCH_LPC_RID_D6:
+ return SocD6;
+ case V_PCH_LPC_RID_D7:
+ return SocD7;
+ default:
+ return SocSteppingMax;
+ }
+}
diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h
index 07b6633..8f5f9a5 100644
--- a/src/soc/intel/braswell/include/soc/ramstage.h
+++ b/src/soc/intel/braswell/include/soc/ramstage.h
@@ -21,6 +21,76 @@
#include <device/device.h>
#include <fsp/ramstage.h>
+#define V_PCH_LPC_RID_A0 0x00 // A0 Stepping
+#define V_PCH_LPC_RID_A1 0x04 // A1 Stepping
+#define V_PCH_LPC_RID_A2 0x08 // A2 Stepping
+#define V_PCH_LPC_RID_A3 0x0C // A3 Stepping
+#define V_PCH_LPC_RID_A4 0x80 // A4 Stepping
+#define V_PCH_LPC_RID_A5 0x84 // A5 Stepping
+#define V_PCH_LPC_RID_A6 0x88 // A6 Stepping
+#define V_PCH_LPC_RID_A7 0x8C // A7 Stepping
+#define V_PCH_LPC_RID_B0 0x10 // B0 Stepping
+#define V_PCH_LPC_RID_B1 0x14 // B1 Stepping
+#define V_PCH_LPC_RID_B2 0x18 // B2 Stepping
+#define V_PCH_LPC_RID_B3 0x1C // B3 Stepping
+#define V_PCH_LPC_RID_B4 0x90 // B4 Stepping
+#define V_PCH_LPC_RID_B5 0x94 // B5 Stepping
+#define V_PCH_LPC_RID_B6 0x98 // B6 Stepping
+#define V_PCH_LPC_RID_B7 0x9C // B7 Stepping
+#define V_PCH_LPC_RID_C0 0x20 // C0 Stepping
+#define V_PCH_LPC_RID_C1 0x24 // C1 Stepping
+#define V_PCH_LPC_RID_C2 0x28 // C2 Stepping
+#define V_PCH_LPC_RID_C3 0x2C // C3 Stepping
+#define V_PCH_LPC_RID_C4 0xA0 // C4 Stepping
+#define V_PCH_LPC_RID_C5 0xA4 // C5 Stepping
+#define V_PCH_LPC_RID_C6 0xA8 // C6 Stepping
+#define V_PCH_LPC_RID_C7 0xAC // C7 Stepping
+#define V_PCH_LPC_RID_D0 0x30 // D0 Stepping
+#define V_PCH_LPC_RID_D1 0x34 // D1 Stepping
+#define V_PCH_LPC_RID_D2 0x38 // D2 Stepping
+#define V_PCH_LPC_RID_D3 0x3C // D3 Stepping
+#define V_PCH_LPC_RID_D4 0xB0 // D4 Stepping
+#define V_PCH_LPC_RID_D5 0xB4 // D5 Stepping
+#define V_PCH_LPC_RID_D6 0xB8 // D6 Stepping
+#define V_PCH_LPC_RID_D7 0xBC // D7 Stepping
+#define B_PCH_LPC_RID_STEPPING_MASK 0xFC // SoC Stepping Mask (Ignoring Package Type)
+
+enum {
+ SocA0 = 0,
+ SocA1 = 1,
+ SocA2 = 2,
+ SocA3 = 3,
+ SocA4 = 4,
+ SocA5 = 5,
+ SocA6 = 6,
+ SocA7 = 7,
+ SocB0 = 8,
+ SocB1 = 9,
+ SocB2 = 10,
+ SocB3 = 11,
+ SocB4 = 12,
+ SocB5 = 13,
+ SocB6 = 14,
+ SocB7 = 15,
+ SocC0 = 16,
+ SocC1 = 17,
+ SocC2 = 18,
+ SocC3 = 19,
+ SocC4 = 20,
+ SocC5 = 21,
+ SocC6 = 22,
+ SocC7 = 23,
+ SocD0 = 24,
+ SocD1 = 25,
+ SocD2 = 26,
+ SocD3 = 27,
+ SocD4 = 28,
+ SocD5 = 29,
+ SocD6 = 30,
+ SocD7 = 31,
+ SocSteppingMax
+};
+
/*
* The soc_init_pre_device() function is called prior to device
* initialization, but it's after console and cbmem has been reinitialized.
@@ -30,6 +100,7 @@
void set_max_freq(void);
void southcluster_enable_dev(device_t dev);
void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);
+int SocStepping(void);
extern struct pci_operations soc_pci_ops;
--
To view, visit https://review.coreboot.org/21371
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f
Gerrit-Change-Number: 21371
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20170904/7740b716/attachment-0001.html>
More information about the coreboot-gerrit
mailing list