<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21371">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/braswell: Add SoC stepping identify helper<br><br>Adapted from Chromium commit 9756af8.<br><br>Add SOC helper to identify BSW SoC stepping. Will be used to<br>override USB2 phy setting based on stepping in subsequent commit.<br><br>Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e<br>Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org><br>Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com><br><br>Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/soc/intel/braswell/chip.c<br>M src/soc/intel/braswell/include/soc/ramstage.h<br>2 files changed, 152 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/21371/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c<br>index 91cb384..e0c1a51 100644<br>--- a/src/soc/intel/braswell/chip.c<br>+++ b/src/soc/intel/braswell/chip.c<br>@@ -169,6 +169,7 @@<br> params->I2C4Frequency = config->I2C4Frequency;<br> params->I2C5Frequency = config->I2C5Frequency;<br> params->I2C6Frequency = config->I2C6Frequency;<br>+<br> }<br> <br> void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,<br>@@ -363,3 +364,83 @@<br> struct pci_operations soc_pci_ops = {<br> .set_subsystem = &pci_set_subsystem,<br> };<br>+<br>+/**<br>+ Return SoC stepping type<br>+<br>+ @retval SOC_STEPPING SoC stepping type<br>+**/<br>+int SocStepping(void)<br>+{<br>+ device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));<br>+ u8 revid = pci_read_config8(dev, 0x8);<br>+<br>+ switch (revid & B_PCH_LPC_RID_STEPPING_MASK) {<br>+ case V_PCH_LPC_RID_A0:<br>+ return SocA0;<br>+ case V_PCH_LPC_RID_A1:<br>+ return SocA1;<br>+ case V_PCH_LPC_RID_A2:<br>+ return SocA2;<br>+ case V_PCH_LPC_RID_A3:<br>+ return SocA3;<br>+ case V_PCH_LPC_RID_A4:<br>+ return SocA4;<br>+ case V_PCH_LPC_RID_A5:<br>+ return SocA5;<br>+ case V_PCH_LPC_RID_A6:<br>+ return SocA6;<br>+ case V_PCH_LPC_RID_A7:<br>+ return SocA7;<br>+ case V_PCH_LPC_RID_B0:<br>+ return SocB0;<br>+ case V_PCH_LPC_RID_B1:<br>+ return SocB1;<br>+ case V_PCH_LPC_RID_B2:<br>+ return SocB2;<br>+ case V_PCH_LPC_RID_B3:<br>+ return SocB3;<br>+ case V_PCH_LPC_RID_B4:<br>+ return SocB4;<br>+ case V_PCH_LPC_RID_B5:<br>+ return SocB5;<br>+ case V_PCH_LPC_RID_B6:<br>+ return SocB6;<br>+ case V_PCH_LPC_RID_B7:<br>+ return SocB7;<br>+ case V_PCH_LPC_RID_C0:<br>+ return SocC0;<br>+ case V_PCH_LPC_RID_C1:<br>+ return SocC1;<br>+ case V_PCH_LPC_RID_C2:<br>+ return SocC2;<br>+ case V_PCH_LPC_RID_C3:<br>+ return SocC3;<br>+ case V_PCH_LPC_RID_C4:<br>+ return SocC4;<br>+ case V_PCH_LPC_RID_C5:<br>+ return SocC5;<br>+ case V_PCH_LPC_RID_C6:<br>+ return SocC6;<br>+ case V_PCH_LPC_RID_C7:<br>+ return SocC7;<br>+ case V_PCH_LPC_RID_D0:<br>+ return SocD0;<br>+ case V_PCH_LPC_RID_D1:<br>+ return SocD1;<br>+ case V_PCH_LPC_RID_D2:<br>+ return SocD2;<br>+ case V_PCH_LPC_RID_D3:<br>+ return SocD3;<br>+ case V_PCH_LPC_RID_D4:<br>+ return SocD4;<br>+ case V_PCH_LPC_RID_D5:<br>+ return SocD5;<br>+ case V_PCH_LPC_RID_D6:<br>+ return SocD6;<br>+ case V_PCH_LPC_RID_D7:<br>+ return SocD7;<br>+ default:<br>+ return SocSteppingMax;<br>+ }<br>+}<br>diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h<br>index 07b6633..8f5f9a5 100644<br>--- a/src/soc/intel/braswell/include/soc/ramstage.h<br>+++ b/src/soc/intel/braswell/include/soc/ramstage.h<br>@@ -21,6 +21,76 @@<br> #include <device/device.h><br> #include <fsp/ramstage.h><br> <br>+#define V_PCH_LPC_RID_A0 0x00 // A0 Stepping<br>+#define V_PCH_LPC_RID_A1 0x04 // A1 Stepping<br>+#define V_PCH_LPC_RID_A2 0x08 // A2 Stepping<br>+#define V_PCH_LPC_RID_A3 0x0C // A3 Stepping<br>+#define V_PCH_LPC_RID_A4 0x80 // A4 Stepping<br>+#define V_PCH_LPC_RID_A5 0x84 // A5 Stepping<br>+#define V_PCH_LPC_RID_A6 0x88 // A6 Stepping<br>+#define V_PCH_LPC_RID_A7 0x8C // A7 Stepping<br>+#define V_PCH_LPC_RID_B0 0x10 // B0 Stepping<br>+#define V_PCH_LPC_RID_B1 0x14 // B1 Stepping<br>+#define V_PCH_LPC_RID_B2 0x18 // B2 Stepping<br>+#define V_PCH_LPC_RID_B3 0x1C // B3 Stepping<br>+#define V_PCH_LPC_RID_B4 0x90 // B4 Stepping<br>+#define V_PCH_LPC_RID_B5 0x94 // B5 Stepping<br>+#define V_PCH_LPC_RID_B6 0x98 // B6 Stepping<br>+#define V_PCH_LPC_RID_B7 0x9C // B7 Stepping<br>+#define V_PCH_LPC_RID_C0 0x20 // C0 Stepping<br>+#define V_PCH_LPC_RID_C1 0x24 // C1 Stepping<br>+#define V_PCH_LPC_RID_C2 0x28 // C2 Stepping<br>+#define V_PCH_LPC_RID_C3 0x2C // C3 Stepping<br>+#define V_PCH_LPC_RID_C4 0xA0 // C4 Stepping<br>+#define V_PCH_LPC_RID_C5 0xA4 // C5 Stepping<br>+#define V_PCH_LPC_RID_C6 0xA8 // C6 Stepping<br>+#define V_PCH_LPC_RID_C7 0xAC // C7 Stepping<br>+#define V_PCH_LPC_RID_D0 0x30 // D0 Stepping<br>+#define V_PCH_LPC_RID_D1 0x34 // D1 Stepping<br>+#define V_PCH_LPC_RID_D2 0x38 // D2 Stepping<br>+#define V_PCH_LPC_RID_D3 0x3C // D3 Stepping<br>+#define V_PCH_LPC_RID_D4 0xB0 // D4 Stepping<br>+#define V_PCH_LPC_RID_D5 0xB4 // D5 Stepping<br>+#define V_PCH_LPC_RID_D6 0xB8 // D6 Stepping<br>+#define V_PCH_LPC_RID_D7 0xBC // D7 Stepping<br>+#define B_PCH_LPC_RID_STEPPING_MASK 0xFC // SoC Stepping Mask (Ignoring Package Type)<br>+<br>+enum {<br>+ SocA0 = 0,<br>+ SocA1 = 1,<br>+ SocA2 = 2,<br>+ SocA3 = 3,<br>+ SocA4 = 4,<br>+ SocA5 = 5,<br>+ SocA6 = 6,<br>+ SocA7 = 7,<br>+ SocB0 = 8,<br>+ SocB1 = 9,<br>+ SocB2 = 10,<br>+ SocB3 = 11,<br>+ SocB4 = 12,<br>+ SocB5 = 13,<br>+ SocB6 = 14,<br>+ SocB7 = 15,<br>+ SocC0 = 16,<br>+ SocC1 = 17,<br>+ SocC2 = 18,<br>+ SocC3 = 19,<br>+ SocC4 = 20,<br>+ SocC5 = 21,<br>+ SocC6 = 22,<br>+ SocC7 = 23,<br>+ SocD0 = 24,<br>+ SocD1 = 25,<br>+ SocD2 = 26,<br>+ SocD3 = 27,<br>+ SocD4 = 28,<br>+ SocD5 = 29,<br>+ SocD6 = 30,<br>+ SocD7 = 31,<br>+ SocSteppingMax<br>+};<br>+<br> /*<br> * The soc_init_pre_device() function is called prior to device<br> * initialization, but it's after console and cbmem has been reinitialized.<br>@@ -30,6 +100,7 @@<br> void set_max_freq(void);<br> void southcluster_enable_dev(device_t dev);<br> void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);<br>+int SocStepping(void);<br> <br> extern struct pci_operations soc_pci_ops;<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/21371">change 21371</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21371"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f </div>
<div style="display:none"> Gerrit-Change-Number: 21371 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>